Voltage detector

• US 8,531,215 B2
• Filed: 11/10/2010
• Issued: 09/10/2013
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Nisshinbo Micro Devices Incorporated
• Original Assignee: Ricoh Company Limited
• Inventors: Morino, Koichi
• Primary Examiner(s): Rojas, Daniel
• Application Number:
  US12/943,592
• Publication Number:
  US 20110121870A1
• Time in Patent Office: 1,035 Days
• Field of Search: 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12

Abstract

A voltage detector includes a first input terminal, a second input terminal, a first voltage detection circuit, a second voltage detection circuit, and a logic holder circuit. The first input terminal receives a first input voltage. The second input terminal receives a second input voltage. The first voltage detection circuit outputs a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage. The second voltage detection circuit outputs a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage. The logic holder circuit retains the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.

Claims

1. A voltage detector comprising:

a first input terminal to receive a first input voltage;

a second input terminal to receive a second input voltage;

a first voltage detection circuit connected to the first input terminal to output a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage;

a second voltage detection circuit connected to the second input terminal to output a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage,

the second detection voltage being lower than the first detection voltage and higher than a minimum operating voltage of the first voltage detection circuit; and

a logic holder circuit having an input thereof connected to the second voltage detection circuit and an output thereof connected to the first voltage detection circuit to retain the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.

2. The voltage detector according to claim 1, further comprising a control circuit connected between the second voltage detection circuit and the logic holder circuit to enable the logic holder circuit by validating the second detection signal when the second input voltage remains below the minimum operating voltage of the first voltage detection circuit, and to disable the logic holder circuit by invalidating the second detection signal when the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

3. The voltage detector according to claim 2, wherein the control circuit comprises:

a third voltage detection circuit connected to the second input terminal to output a third detection signal that switches a logic state thereof when the second input voltage falls below a third detection voltage; and

a logic circuit connected to the outputs of the first through third voltage detection circuits to control the second detection signal according to the first and third detection signals.

4. The voltage detector according to claim 1, wherein the voltage detector enables the logic holder circuit by validating the second detection signal when the second input voltage remains below the minimum operating voltage of the first voltage detection circuit, and disables the logic holder circuit by invalidating the second detection signal when the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

5. The voltage detector according to claim 1, further comprising a control circuit connected between the second voltage detection circuit and the logic holder circuit to initially enable the logic holder circuit by validating the second detection signal until the second input voltage exceeds the minimum operating voltage of the first voltage detection circuit, and to subsequently disable the logic holder circuit by invalidating the second detection signal once the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

6. The voltage detector according to claim 5, wherein the control circuit comprises:

an RS flip-flop;

a first one-shot pulse generator connected to the second input terminal to generate an electrical pulse for input to the RS flip-flop as the second input voltage rises to an operating voltage;

a second one-shot pulse generator connected to the output of the first voltage detection circuit to generate an electrical pulse for input to the RS flip-flop when the first detection signal switches to assert a reset signal; and

a logic circuit connected to the outputs of the first and second voltage detection circuits and the RS flip-flop to control the second detection signal according to an output of the RS flip-flop and the first detection signal.

7. The voltage detector according to claim 1, wherein the voltage detector initially enables the logic holder circuit by validating the second detection signal until the second input voltage exceeds the minimum operating voltage of the first voltage detection circuit, and subsequently disables the logic holder circuit by invalidating the second detection signal once the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

8. The voltage detector according to claim 1, further comprising a delay circuit connected between the second voltage detection circuit and the logic holder circuit to provide a delay time between when the second detection signal switches the logic state thereof and when the logic holder circuit retains the logic state of the first detection signal.

9. The voltage detector according to claim 1, wherein the voltage detector exhibits a delay time between when the second detection signal switches the logic state thereof and when the logic holder circuit retains the logic state of the first detection signal.

10. The voltage detector according to claim 1, further comprising a step-down voltage regulator that converts a power supply voltage into a lower constant voltage for supply to the first and second voltage detection circuits,

wherein the voltage detector is integrated into a single integrated circuit powered with the power supply voltage.

11. The voltage detector according to claim 10, further comprising a control circuit connected between the second voltage detection circuit and the logic holder circuit to enable the logic holder circuit by validating the second detection signal when the power supply voltage remains below the minimum operating voltage of the first voltage detection circuit, and to disable the logic holder circuit by invalidating the second detection signal when the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

12. The voltage detector according to claim 11, wherein the control circuit comprises:

a third voltage detection circuit connected to the second input terminal to output a third detection signal that switches a logic state thereof when the second input voltage falls below a third detection voltage; and

a logic circuit connected to the outputs of the first through third voltage detection circuits to control the second detection signal according to the first and third detection signals.

13. The voltage detector according to claim 10, wherein the voltage detector enables the logic holder circuit by validating the second detection signal when the power supply voltage remains below the minimum operating voltage of the first voltage detection circuit, and disables the logic holder circuit by invalidating the second detection signal when the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

14. The voltage detector according to claim 10, further comprising a control circuit connected between the second voltage detection circuit and the logic holder circuit to initially enable the logic holder circuit by validating the second detection signal until the power supply voltage exceeds the minimum operating voltage of the first voltage detection circuit, and to subsequently disable the logic holder circuit by invalidating the second detection signal once the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.

15. The voltage detector according to claim 14, wherein the control circuit comprises:

an RS flip-flop;

a first one-shot pulse generator connected to the second input terminal to generate an electrical pulse for input to the RS flip-flop as the second input voltage rises to an operating voltage;

a second one-shot pulse generator connected to the output of the first voltage detection circuit to generate an electrical pulse for input to the RS flip-flop when the first detection signal switches to assert a reset signal; and

a logic circuit connected to the outputs of the first and second voltage detection circuits and the RS flip-flop to control the second detection signal according to an output of the RS flip-flop and the first detection signal.

16. The voltage detector according to claim 10, wherein the voltage detector initially enables the logic holder circuit by validating the second detection signal until the power supply voltage exceeds the minimum operating voltage of the first voltage detection circuit, and subsequently disables the logic holder circuit by invalidating the second detection signal once the first detection signal indicates that the first input voltage reaches the first detection voltage to assert a reset signal.