Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines
First Claim
1. A method of forming a series of capacitorless one transistor DRAM cells, comprising:
- forming a series of spaced islands of semiconductive material relative to a substrate;
forming a word line which extends over the series of spaced islands, the word line being formed over and capacitively coupled to an electrically floating body region of the respective spaced islands;
forming a pair of conductively interconnected gate lines extend at least partially over the series of spaced islands on opposite sides of the word line and which are electrically isolated from the word line, the pair of gates lines being received over and capacitively coupled to respective floating body regions of the respective spaced islands; and
forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the pair of gate lines.
7 Assignments
0 Petitions
Accused Products
Abstract
This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.
332 Citations
27 Claims
-
1. A method of forming a series of capacitorless one transistor DRAM cells, comprising:
-
forming a series of spaced islands of semiconductive material relative to a substrate; forming a word line which extends over the series of spaced islands, the word line being formed over and capacitively coupled to an electrically floating body region of the respective spaced islands; forming a pair of conductively interconnected gate lines extend at least partially over the series of spaced islands on opposite sides of the word line and which are electrically isolated from the word line, the pair of gates lines being received over and capacitively coupled to respective floating body regions of the respective spaced islands; and forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the pair of gate lines. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of forming a series of capacitorless one transistor DRAM cells, comprising:
-
forming a series of spaced islands of semiconductive material relative to a substrate; forming a word line which extends over the series of spaced islands, the word line being formed over and capacitively coupled to an electrically floating body region of the respective spaced islands and comprising an end; forming a pair of conductively interconnected gate lines which extend at least partially over the series of spaced islands on opposite sides of the word line and which are electrically isolated from the word line, the pair of gates lines being received over and capacitively coupled to respective floating body regions of the respective spaced islands, respective ends of the pair of gate lines being proximate the word line end, the patterning resulting in the word line extending longitudinally beyond the respective ends of the pair of gate lines; and forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the pair of gate lines. - View Dependent Claims (9, 10, 11)
-
-
12. A method of forming a series of capacitorless one transistor DRAM cells, comprising:
-
forming a series of spaced islands of silicon-comprising semiconductive material relative to a substrate; forming a word line which is common to and extends over the line of spaced islands, the word line being formed over an electrically floating body region of the respective spaced islands; forming a conductive layer over and spaced from the word line; forming a masking block over the conductive layer and the word line, the masking block having spaced opposing lateral edges; after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the conductive layer; after the heating, etching the conductive layer using the masking block as a mask to form a pair of interconnected gate lines which are common to and extend over the series of spaced islands on opposite sides of the word line, the pair of gates lines being received over respective floating body regions of the respective spaced islands; and forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the interconnected pair of gate lines.
-
-
13. A method of patterning a substrate, comprising:
-
forming a raised feature relative to a substrate, the raised feature comprising a top and opposing sidewalls; forming a layer to be patterned over the top and opposing sidewalls of the raised feature; forming a masking block over the layer, the masking block having spaced opposing lateral edges that are received laterally inward of the opposing sidewalls of the raised feature; after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the layer and laterally outward beyond the opposing sidewalls of the raised feature; and after the heating, etching the layer using the masking block as a mask to leave the layer received over the top and opposing sidewalls of the raised feature. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
-
20. A method of forming two conductive lines, comprising:
-
forming a raised first conductive line over a substrate; insulating a top and sidewalls of the raised conductive line; forming conductive material over the insulated top of the raised first conductive line; forming a masking block over the conductive material, the masking block having spaced opposing lateral edges; after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the conductive material; and after the heating, etching the conductive material using the masking block as a mask to form a second conductive line over and electrically isolated from the first conductive line. - View Dependent Claims (21, 22, 23, 24, 25)
-
-
26. A method of patterning a substrate, comprising:
-
forming a raised feature relative to a substrate; forming a layer to be patterned over the raised feature, an outer surface of the layer having laterally opposed curved portions where the outer surface curves to extend elevationally inward along opposing sidewalls of the raised feature; forming a masking block over the layer, the masking block having spaced opposing lateral edges; after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the layer, the opposing lateral edges each being moved laterally outward to the laterally opposed curved portions of the outer surface of the layer; and after the heating, etching the layer using the masking block as a mask to leave the layer received over the raised feature. - View Dependent Claims (27)
-
Specification