QoS-aware scheduling

• US 8,553,042 B2
• Filed: 10/16/2012
• Issued: 10/08/2013
• Est. Priority Date: 09/16/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Biswas, Sukalpa, Chen, Hao
• Primary Examiner(s): Martello, Edward
• Application Number:
  US13/653,109
• Publication Number:
  US 20130046938A1
• Time in Patent Office: 357 Days
• Field of Search: 345/531
• US Class Current: 345/531
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 9/5033 considering data affinity

Abstract

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Claims

1. A memory controller comprising:

an agent interface unit coupled to receive a plurality of memory operations from one or more sources, and wherein each memory operation of the plurality of memory operations is accompanied by a quality of service (QoS) parameter specifying a requested quality of service for the memory operation, wherein the agent interface unit comprises at least one memory channel interface unit configured to schedule the memory operations to access the memory, wherein scheduling decisions in the memory channel interface unit are responsive to the QoS parameters associated with the memory operations; and

at least one memory channel unit coupled to receive the memory operations scheduled by the memory channel interface unit, and wherein the memory channel unit is configured to schedule read operations responsive to the QoS parameters, and wherein, in a first case, the memory channel unit is configured to rank a low-latency QoS parameter equal to a best effort QoS parameter, and wherein, in a second case, the memory channel unit is configured to rank the low-latency QoS parameter higher than the best effort QoS parameter.

2. The memory controller as recited in claim 1 wherein the plurality of memory operations comprise operations of at least two types, wherein the QoS parameters are defined differently for each of the types, and wherein the memory channel interface unit is configured to rank the differently-defined QoS parameters with respect to each other in order to make the scheduling decisions.

3. The memory controller as recited in claim 2 wherein the at least two types include a real time (RT) type and a non-real time (NRT) type, and wherein the best effort QoS parameter and the low latency QoS parameter are associated with the NRT type.

4. The memory controller as recited in claim 3 and wherein the memory channel interface unit is configured to rank at least some of the QoS parameters associated with the RT type above the QoS parameters associated with the NRT type.

5. The memory controller as recited in claim 3, and wherein the memory channel unit is configured to rank a lowest parameter of the RT type equal to the best effort QoS parameter and the low latency QoS parameter.

6. The memory controller as recited in claim 5 wherein the memory channel interface unit is configured to rank a highest level of the RT type above all levels of the NRT type.

7. The memory controller as recited in claim 6 wherein the memory channel interface unit is configured to rank a middle level of RT type above all levels of the NRT type.

8. The memory controller as recited in claim 7 wherein a difference between the first case and the second case is a number of operations in a queue within the memory channel unit.

9. A memory controller comprising:

an agent interface unit coupled to receive a plurality of memory operations from one or more sources, wherein each memory operation of the plurality of memory operations is accompanied by a quality of service (QoS) parameter specifying a requested quality of service for the memory operation, wherein the plurality of memory operations are classified into one of at least two traffic classes, wherein the QoS parameter definition is different for the different traffic classes; and

a plurality of memory channel units, each of the plurality of memory channel units configured to interface to memory on a respective memory channel of the plurality of memory channels;

wherein the agent interface unit is configured to identify a memory channel of the plurality of memory channels for each memory operation of the plurality of memory operations, wherein the identified memory channel is the memory channel to which the memory operation is directed, and wherein the agent interface unit is configured to independently schedule memory operations to each memory channel unit, and wherein scheduling decisions among memory operations directed to a particular memory channel are responsive, at least in part, to the QoS parameters of the memory operations, and wherein the ranking of the QoS parameters of each traffic class with respect to the QoS parameters of other traffic classes is dependent on a state of the memory controller.

10. The memory controller as recited in claim 9 wherein the at least two traffic classes include a real time (RT) class and a non-real time (NRT) class, and wherein the memory channel interface units are configured to rank at least some parameter levels of the RT class higher than the parameter levels of the NRT class.

11. The memory controller as recited in claim 10 wherein the parameter levels of the NRT class include a best effort level and a low latency level, and wherein the plurality of memory channel units and configured to rank the best effort level and the low latency level at a same level in one case, and to rank the low latency level higher than the best effort level in another case.

12. The memory controller as recited in claim 11 wherein a difference between the first case and the second case is a number of memory operations awaiting scheduling in a given one of the plurality of memory channel units.

13. The memory controller as recited in claim 11 wherein the plurality of memory channel units are configured to rank a lowest parameter level of the RT class equal to the low latency level.

14. The memory controller as recited in claim 13 wherein the plurality of memory channel units are configured to eliminate the QoS class for write memory operations and to rank write memory operations with respect to read memory operations dependent on write queue fullness.

15. A method comprising:

receiving a plurality of memory operations in a memory controller, wherein each memory operation of the plurality of memory operations has an associated quality of service (QoS) parameter indicating a requested quality of service for the memory operation, and wherein each of the plurality of memory operations has an associated traffic class, wherein the associated QoS parameter is defined according to the associated traffic class; and

scheduling memory operations directed to each memory channel of a plurality of memory channels according to the QoS parameters associated with the memory operations and further according to a state of the memory controller, wherein a relative ranking of the QoS parameters is different for different states of the memory controller.

16. The method as recited in claim 15 further comprising:

a memory channel unit associated with each memory channel queuing memory operations for that channel in read queues and write queues;

the memory channel unit dropping the QoS parameters of write operations; and

the memory channel unit scheduling the write operations with respect to read operations based on write queue fullness.

17. The method as recited in claim 16 further comprising the memory channel unit scheduling read operations based on the QoS parameters of the read operations.

18. The method as recited in claim 17 wherein scheduling comprises equating a lowest level of real time (RT) QoS levels with a lowest level of non-real time (NRT) QoS levels.

19. The method as recited in claim 15 wherein the associated traffic class defines a low latency level and a best effort level, and wherein the relative ranking of the low latency level and the best effort level are the same in one state and different in another state of the memory controller.

20. The method as recited in claim 19 wherein the states of the memory controller differ in terms of a number of queued memory operations in the memory controller.