Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

• US 8,553,470 B2
• Filed: 03/14/2011
• Issued: 10/08/2013
• Est. Priority Date: 05/08/2003
• Status: Active Grant

• Current Assignee: JEDDELOH, JOSEPH M., LEE, TERRY R., Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Terry R., Jeddeloh, Joseph M.
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/047,602
• Publication Number:
  US 20110164446A1
• Time in Patent Office: 939 Days
• Field of Search: 365/189.02, 365/189.04, 365/230.02, 365/230.06, 365/238.5
• US Class Current: 365/189.04
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09972 Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Claims

1. A method of accessing and processing data in memory comprising a plurality of electrically isolated sectors, each sector comprising at least one memory device, the method comprising:

receiving at two or more memory devices of different sectors respective control and address signals;

processing the respective control and address signals; and

simultaneously accessing the two or more memory devices of different sectors based on the respective control and address signals.

2. The method of claim 1, wherein processing the control and address signals comprises multiplexing data signals.

3. The method of claim 1, wherein processing the control and address signals comprises de-multiplexing data signals.

4. The method of claim 1, wherein processing the control and address signals comprises encoding data signals.

5. The method of claim 1, wherein processing the control and address signals comprises decoding data signals.

6. A method of accessing and processing data in a memory comprising a plurality of memory devices organized into a plurality of memory ranks, each memory rank comprising a plurality of electrically isolated memory devices, the method comprising:

receiving at two or more electrically isolated memory devices of one or more memory ranks respective control and address signals;

processing the respective control and address signals; and

simultaneously accessing the two or more electrically isolated memory devices of one or more memory ranks based on the respective control and address signals.

7. The method of claim 6, wherein receiving control and address signals comprise receiving control and address signals at a driver chip.

8. The method of claim 6, wherein receiving control and address signals comprises receiving control and address signals at a plurality of driver chips.

9. The method of claim 6, wherein simultaneously accessing two or more memory devices of one or more memory comprises simultaneously writing to the two or more memory devices of the one or more memory ranks based on the control and address signals.

10. The method of claim 6, wherein simultaneously accessing two or more memory devices of one or more memory comprises simultaneously reading from the two or more memory devices of the one or more memory ranks based on the control and address signals.

11. The method of claim 6, wherein the control and address signals comprise optical signals.

12. The method of claim 6, wherein the control and address signals comprise RF signals.

13. A method of accessing and processing data in a memory comprising a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a plurality of electrically-isolated memory devices, the method comprising:

receiving at two or more memory ranks respective control and address signals;

processing the respective control and address signals; and

simultaneously accessing the two or more memory ranks based on the respective control and address signals.

14. The method of claim 13 wherein simultaneously accessing two or more memory ranks comprises simultaneously accessing a first memory device of a first sector and a second memory device of a second sector, the first and second memory devices associated with a first rank, the first and second memory devices of the first and second sectors electrically-isolated.

15. The method of claim 13 wherein simultaneously accessing two or more memory ranks comprises simultaneously accessing memory devices of a first sector and accessing memory devices of a second sector, the memory devices of the first sector associated with a first rank and the memory devices of the second sector associated with a second rank, the memory devices of the first sector electrically-isolated from the memory devices of the second sector.

16. The method of claim 13 wherein simultaneously accessing two or more memory ranks based comprises independently and simultaneously accessing two or more memory ranks.

17. The method of claim 13 wherein receiving control and address signals comprises receiving independent control and address signals for each memory rank.

18. The method of claim 13 wherein processing the control and address signals comprises processing the control and address signals at a respective driver for each memory rank.

19. The method of claim 13 wherein receiving control and address signals comprises receiving control and address signals for a first memory rank at a first driver associated with the first memory rank and receiving control and address signals for a second memory rank at a second driver associated with the second memory rank.

20. A method of accessing and processing data in a memory comprising a plurality of memory devices segmented into a plurality of electrically-isolated memory sectors, each memory sector comprising a plurality of memory devices, the method comprising:

receiving at two or more memory sectors respective control and address signals;

processing the respective control and address signals; and

simultaneously accessing the two or more memory sectors based on the respective control and address signals.

21. The method of claim 20 wherein simultaneously accessing two or more memory sectors comprises independently and simultaneously accessing two or more memory sectors based on the control and address signals.

22. The method of claim 20 wherein simultaneously accessing two or more memory sectors comprises executing a high peak current event on a memory device of a first sector out of phase with executing a sensitive event on a memory device of a second sector different from the first sector.