Thin film transistors having multi-layer channel

• US 8,558,323 B2
• Filed: 09/23/2010
• Issued: 10/15/2013
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Park, Young-soo, Park, Jae-chul
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US12/923,472
• Publication Number:
  US 20110042669A1
• Time in Patent Office: 1,118 Days
• Field of Search: 257/43, 257/E29.291, 257/E29.294
• US Class Current: 257/404
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.

Claims

1. A thin film transistor, comprising:

a gate insulating layer;

a gate electrode formed on a bottom side of the gate insulating layer;

a channel layer formed on a top side of the gate insulating layer;

a source electrode that contacts a first portion of the channel layer; and

a drain electrode that contacts a second portion of the channel layer;

wherein the channel layer has a double-layer structure, including an uppermost layer and a lower layer, the lower layer being disposed between the uppermost layer and the gate insulating layer,

wherein the uppermost layer has a carrier concentration lower than that of the lower layer, and

wherein the uppermost layer is doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.

2. The transistor of claim 1, wherein the channel layer is formed of a ZnO based material.

3. The transistor of claim 1, wherein the channel layer is formed of a(In₂O₃).b(Ga₂O₃).c(ZnO), and

where a, b, and c are real numbers such that a≧

0, b≧

0, and c>

0.

4. The transistor of claim 1, wherein the carrier acceptor comprises one or more of Cu, Ag, Li, Na, K, Mg, Ca, Be, Au, Rg, Ni, Co, Rh, Pd, Ir, Pt, V, Nb, Ta, and N.

5. The transistor of claim 4, wherein the carrier acceptor comprises Cu, and

wherein the Cu content of the uppermost layer is 29-44 atomic %.

6. The transistor of claim 5, wherein a thickness of the uppermost layer is greater than or equal to 10 nm and less than or equal to 100 nm.