System and method for executing functional scanning in an integrated circuit environment

• US 8,560,903 B2
• Filed: 08/31/2010
• Issued: 10/15/2013
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Wang, Zhiyuan, Gu, Xinli, Wang, Zhanglei, Fang, Hongxia
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/873,135
• Publication Number:
  US 20120053924A1
• Time in Patent Office: 1,141 Days
• Field of Search: 714/724, 714/726, 714/731, 714/741, 714/744
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with the integrated circuit. A functional state of the integrated circuit is locked when the failure occurs, and the functional state is subsequently recovered for a structure test for the integrated circuit. In more particular embodiments, particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

Claims

1. A method, comprising:

executing a functional test for an integrated circuit;

observing a failure associated with the integrated circuit; and

executing a functional scan mode in order to reproduce the failure associated with the integrated circuit, wherein a functional state of the integrated circuit is locked when the failure occurs, and wherein the functional state is subsequently recovered for a structure test for the integrated circuit.

2. The method of claim 1, wherein particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

3. The method of claim 2, further comprising:

utilizing a clock control a state recover element in order to transfer a state associated with the model circuit into the integrated circuit being tested.

4. The method of claim 1, wherein partitioning is executed in order to identify particular intervals in which the failure occurs.

5. The method of claim 1, further comprising:

executing failure searching in order to identify appropriate time intervals in which the failure can be observed, wherein a trigger state that caused the failure associated with integrated circuit is identified.

6. The method of claim 1, further comprising:

performing a diagnosis based on fault models developed in conjunction with executing the functional scan mode for the integrated circuit.

7. The method of claim 1, wherein functional test power and noise conditions are reproduced for the structure test for the integrated circuit.

8. Non-transitory computer readable media that includes code for execution and when executed by a processor perform operations comprising:

executing a functional test for an integrated circuit;

observing a failure associated with the integrated circuit; and

executing a functional scan mode in order to reproduce the failure associated with the integrated circuit, wherein a functional state of the integrated circuit is locked when the failure occurs, and wherein the functional state is subsequently recovered for a structure test for the integrated circuit.

9. The media of claim 8, wherein particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

10. The media of claim 9, the operations further comprising:

utilizing a clock control a state recover element in order to transfer a state associated with the model circuit into the integrated circuit being tested.

11. The media of claim 8, wherein partitioning is executed in order to identify particular intervals in which the failure occurs.

12. The media of claim 8, the operations further comprising:

executing failure searching in order to identify appropriate time intervals in which the failure can be observed.

13. The media of claim 8, the operations further comprising:

performing a diagnosis based on fault models developed in conjunction with executing the functional scan mode for the integrated circuit.

14. The media of claim 8, wherein functional test power and noise conditions are reproduced for the structure test for the integrated circuit.

15. An apparatus, comprising:

an integrated circuit that includes a clock controller coupled to core logic and to a circuit state element, wherein the apparatus is configured to;

execute a functional test for an integrated circuit;

observe a failure associated with the integrated circuit; and

execute a functional scan mode in order to reproduce the failure associated with the integrated circuit, wherein a functional state of the integrated circuit is locked when the failure occurs, and wherein the functional state is subsequently recovered for a structure test for the integrated circuit.

16. The apparatus of claim 15, wherein particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

17. The apparatus of claim 16, wherein the clock controller and the circuit state element are used to transfer a state associated with the model circuit into the integrated circuit being tested.

18. The apparatus of claim 15, wherein partitioning is executed in order to identify particular intervals in which the failure occurs.

19. The apparatus of claim 15, wherein the apparatus is further configured to:

execute failure searching in order to identify appropriate time intervals in which the failure can be observed.

20. The apparatus of claim 15, the apparatus being further configured to:

perform a diagnosis based on fault models developed in conjunction with executing the functional scan mode for the integrated circuit, wherein functional test power and noise conditions are reproduced for the structure test for the integrated circuit.