Pipelined parallelization with localized self-helper threading

• US 8,561,046 B2
• Filed: 09/14/2009
• Issued: 10/15/2013
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Song, Yonghong, Kalogeropulos, Spiros, Tirumalai, Partha P.
• Primary Examiner(s): Zhen, Li B
• Assistant Examiner(s): COYER, RYAN D
• Application Number:
  US12/559,167
• Publication Number:
  US 20110067014A1
• Time in Patent Office: 1,492 Days
• Field of Search: 717/161
• US Class Current: 717/161
• CPC Class Codes: G06F 8/456 Parallelism detection

Abstract

A system and method for automatically parallelizing a computer program for multi-threaded execution. A compiler identifies and parallelizes non-DOALL parallel regions, such as loops, within a computer program. The compiler determines enhanced helper thread instructions based upon the main body instructions of the non-DOALL region. These helper thread instructions are inserted ahead of the main body instructions within each of the plurality of threads, rather than within a single main thread. Next, synchronization instructions are inserted in one or more threads such that the main body of work of each thread is performed in a pipelined manner. The helper thread instructions within each thread may reduce the total execution time of each thread.

Claims

1. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:

identify a parallel region with cross-iteration dependences within program instructions of a computer program;

parallelize the parallel region into a plurality of threads, wherein each of said threads comprises a same set of algorithmic instructions;

generate helper thread instructions based at least in part on the algorithmic instructions;

insert the helper thread instructions in each of the plurality of threads;

insert synchronization instructions in one or more of the plurality of threads, wherein the synchronization instructions are configured to cause execution of the algorithmic instructions of each of the plurality of threads to occur in program order with respect to each other thread of the plurality of threads;

determine that a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions; and

set a next output of the second instruction to have a same value as that of a previous output of the second instruction in response to predicting that the second instruction will not be executed.

2. The storage medium as recited in claim 1, wherein the program instructions are further executable to insert the helper thread instructions ahead of the algorithmic instructions within each of the plurality of threads, and wherein the helper thread instructions are configured to begin simultaneous execution with respect to each other thread of the plurality of threads.

3. The storage medium as recited in claim 2, wherein the program instructions are further executable to determine a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions of a previous logical thread of the plurality of threads.

4. The storage medium as recited in claim 3, wherein the program instructions are further executable to insert a synchronization instruction ahead of said first instruction configured to halt execution of said first instruction until said second instruction completes, in response to said determination.

5. The storage medium as recited in claim 3, wherein in response to determining a total execution time of the helper thread instructions is greater than a total execution time of the algorithmic instructions, the program instructions are further executable to insert instructions ahead of the helper thread instructions configured to:

halt execution of the helper thread instructions until initial values used to compute an output of said second instruction are indicated as ready from a previous logical thread of the plurality of threads;

compute a next output of said second instruction using the ready initial values, and convey said next output to the first instruction; and

convey an indication that an output of said second instruction is ready to a subsequent logical thread of the plurality of threads.

6. The storage medium as recited in claim 3, wherein the program instructions are further executable to set a next output of said second instruction to have a same value as that of a previous output of the second instruction immediately before a conditional expression, in response to predicting the second instruction will not be executed.

7. The storage medium as recited in claim 2, wherein said helper thread instructions may perform at least one of the following:

address calculations for load and store operations, data cache prefetching, and early branch prediction resolution.

8. The storage medium as recited in claim 2, wherein identifying a parallel region comprises detecting one or more of the following:

a loop construct instruction, a user-specified directive, a first function call with no data dependencies on a second function call, and a first basic block with no data dependencies on a second basic block.

9. A compilation method for automatically parallelizing a computer program executable by a processor comprising:

identifying a parallel region with cross-iteration dependences within program instructions of a computer program;

parallelizing the parallel region into a plurality of threads, wherein each thread comprises a same set of algorithmic instructions;

generating helper thread instructions based at least in part on the algorithmic instructions;

inserting the helper thread instructions in each of the plurality of threads; and

inserting synchronization instructions in one or more of the plurality of threads, wherein the synchronization instructions are configured to cause execution of the algorithmic instructions of each of the plurality of threads to occur in program order with respect to each other thread of the plurality of threads;

determining that a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions; and

setting a next output of the second instruction to have a same value as that of a previous output of the second instruction in response to predicting that the second instruction will not be executed.

10. The method as recited in claim 9, further comprising inserting the helper thread instructions ahead of the algorithmic instructions within each of the plurality of threads, and wherein the helper thread instructions are configured to begin simultaneous execution with respect to each other thread of the plurality of threads.

11. The method as recited in claim 10, further comprising determining a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions of a previous logical thread of the plurality of threads.

12. The method as recited in claim 11, further comprising, in response to said determination, inserting a synchronization instruction ahead of said first instruction configured to halt execution of said first instruction until said second instruction completes.

13. The method as recited in claim 11, in response to determining a total execution time of the helper thread instructions is greater than a total execution time of the algorithmic instructions, further comprising:

halting execution of the helper thread instructions until initial values used to compute an output of said second instruction are indicated as ready from a previous logical thread of the plurality of threads;

computing a next output of said second instruction using the ready initial values; and

conveying an indication that an output of said second instruction is ready to a subsequent logical thread of the plurality of threads.

14. The method as recited in claim 11, further comprising setting a next output of said second instruction to have a same value as that of a previous output of the second instruction immediately before a conditional expression, in response to predicting the second instruction will not be executed.

15. The method as recited in claim 10, wherein said helper thread instructions may perform at least one of the following:

address calculations for load and store operations, data cache prefetching, and early branch prediction resolution.

16. The method as recited in claim 10, wherein identifying a parallel region comprises detecting one or more of the following:

a loop construct instruction, a user-specified directive, a first function call with no data dependencies on a second function call, and a first basic block with no data dependencies on a second basic block.

17. A compiler comprising:

a processor;

a memory coupled to the processor;

code generation instructions stored in the memory and executed by the processor; and

optimization instructions stored in the memory and executed by the processor, the optimization instructions configured to;

identify a parallel region with cross-iteration dependences within program instructions of a computer program;

parallelize the parallel region into a plurality of threads, wherein each thread comprises a same set of algorithmic instructions; and

determine helper thread instructions based upon the algorithmic instructions; and

wherein the code generation instructions are configured to;

insert the helper thread instructions in each of the plurality of threads; and

insert synchronization instructions in one or more of the plurality of threads, wherein the synchronization instructions are configured to cause execution of the algorithmic instructions of each of the plurality of threads to occur in program order with respect to each other thread of the plurality of threads; and

wherein the optimization instructions are further configured to;

determine that a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions; and

to set a next output of said second instruction to have a same value as that of a previous output of the second instruction in response to predicting that the second instruction will not be executed.

18. The compiler as recited in claim 17, wherein the code generation instructions are further configured to insert the helper thread instructions ahead of the algorithmic instructions within each of the plurality of threads, and wherein the helper thread instructions are configured to begin simultaneous execution with respect to each other thread of the plurality of threads.

19. The compiler as recited in claim 18, wherein the optimization instructions are further configured to determine a first instruction of the helper thread instructions is dependent upon a second instruction of the helper thread instructions of a previous logical thread of the plurality of threads.

20. The compiler as recited in claim 19, wherein the optimization instructions are further executable to, in response to said determination, insert a synchronization instruction ahead of said first instruction configured to halt execution of said first instruction until said second instruction completes.