Command interface systems and methods

• US 8,572,292 B2
• Filed: 08/19/2011
• Issued: 10/29/2013
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ito, Yutaka, Yamamoto, Tadashi
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MODO, RONALD T
• Application Number:
  US13/213,997
• Publication Number:
  US 20110302328A1
• Time in Patent Office: 802 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Claims

1. A method comprising:

executing internal commands with a command decoder in an electronic device during a sleep mode of operation of the electronic device;

receiving external command signals in the electronic device to indicate an end of the sleep mode of operation;

disabling the command decoder with a signal generated by the electronic device in response to the external command signals during a transfer period between the first sleep mode of operation and a normal mode of operation of the electronic device; and

executing external commands with the command decoder in the electronic device during the normal mode of operation of the electronic device following the transfer period.

2. The method of claim 1, wherein executing the commands with the command decoder in the electronic device during the sleep mode of operation further comprises:

decoding internal command signals into internal commands in the command decoder in a memory device; and

executing the internal commands during the sleep mode of operation of the memory device.

3. The method of claim 1, wherein executing external commands with the command decoder in the electronic device during the normal mode of operation further comprises:

decoding the external command signals into the external commands in the command decoder in a memory device; and

executing the external commands during the normal mode of operation of the memory device.

4. The method of claim 1, wherein disabling the command decoder includes disabling the command decoder when an internal chip select signal operates to disable the command decoder in the electronic device.

5. A method comprising:

executing internal commands with a command decoder in an electronic device during a sleep mode of operation;

generating an internal disable command in the electronic device;

disabling the command decoder with the internal disable command during a transfer period between the sleep mode of operation and a normal mode of operation; and

executing external commands with the command decoder in the electronic device during the normal mode of operation following the transfer period.

6. The method of claim 5, further comprising generating the internal commands in the electronic device.

7. The method of claim 6, wherein executing the internal commands includes executing the internal commands with the command decoder in the electronic device before the transfer period.

8. The method of claim 5, further comprising receiving the external commands in the electronic device.

9. The method of claim 8, wherein executing the external commands includes executing the external commands with the command decoder in the electronic device following the transfer period.

10. An apparatus comprising:

a command decoder in an electronic device to decode and execute internal commands within the electronic device during a sleep mode of operation and to decode and execute external commands during a normal mode of operation; and

a controller in the electronic device to generate a disable command to disable the command decoder during a transfer period between the sleep mode of operation and the normal mode of operation.

11. The apparatus of claim 10, wherein the controller is structured to generate the internal commands executed by the command decoder during the sleep mode of operation.

12. The apparatus of claim 11, wherein the controller comprises an error correcting code controller circuit to generate internal command signals during the sleep mode of operation, the command decoder to decode the internal command signals into the internal commands.

13. The apparatus of claim 10, further comprising a circuit in the electronic device to generate an internal chip select signal to disable the command decoder during the transfer period.

14. An apparatus comprising:

an array of memory cells in a memory device;

a command decoder in the memory device to decode and execute internal commands during a sleep mode of operation and to decode and execute external commands during a normal mode of operation with respect to the memory cells in the array; and

a controller in the memory device, the controller structured to generate a disable command to disable the command decoder during a transfer period between the sleep mode of operation and the normal mode of operation.

15. The apparatus of claim 14, wherein the controller is coupled to the command decoder to generate a chip select signal during the transfer period to disable the command decoder.

16. The apparatus of claim 14, wherein the controller comprises an error correcting code controller circuit coupled to generate internal command signals during the sleep mode of operation.

17. The apparatus of claim 14, further comprising a state machine in the memory device to generate control signals to control operations of the memory device during the sleep mode of operation.

18. A method comprising:

generating internal commands in an electronic device during a sleep mode of operation;

executing the internal commands with a command decoder in the electronic device during the sleep mode of operation of the electronic device;

receiving external commands in the electronic device during a normal mode of operation;

executing the external commands with the command decoder during the normal mode of operation of the electronic device; and

disabling the command decoder in the electronic device when changing between the sleep mode of operation and the normal mode of operation of the electronic device.

19. The method of claim 18, wherein disabling the command decoder further comprises suspending execution of the internal commands in the electronic device between an end of the sleep mode of operation and a beginning of the normal mode of operation.

20. The method of claim 19, wherein the electronic device comprises a memory device.