Uniformity control for IC passivation structure

• US 8,581,389 B2
• Filed: 05/27/2011
• Issued: 11/12/2013
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Yu, Tsung-Yuan
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US13/117,641
• Publication Number:
  US 20120299167A1
• Time in Patent Office: 900 Days
• Field of Search: None
• US Class Current: 257/700
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]

Abstract

The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.

Claims

1. A semiconductor device, comprising:

a wafer containing an interconnect structure, the interconnect structure including a plurality of vias and interconnect lines;

a first conductive pad disposed over the interconnect structure, the first conductive pad being electrically coupled to the interconnect structure;

a plurality of second conductive pads disposed over the interconnect structure;

passivation layer disposed over and at least partially sealing the first and second conductive pads;

a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads; and

a first post-passivation interconnect (PPI) device disposed over the passivation layer, wherein the first PPI device is electrically coupled to the first conductive pad, and wherein the first PPI device is electrically coupled to the conductive terminal.

2. The semiconductor device of claim 1, wherein:

the wafer contains a plurality of electronic components;

the first conductive pad is electrically coupled to at least one of the electronic components through the interconnect structure; and

the second conductive pads are not electrically coupled to the electronic components.

3. The semiconductor device of claim 1, further including:

a plurality of second PPI devices disposed over the passivation layer, wherein none of the second PPI devices are electrically coupled to the first conductive pad, and wherein none of the second PPI devices are electrically coupled to the conductive terminal.

4. The semiconductor device of claim 3, wherein the conductive terminal includes a solder ball.

5. The semiconductor device of claim 3. wherein the first and second conductive pads have the same material composition, and wherein the first and second PPI devices have the same material composition.

6. The semiconductor device, of claim 3, wherein:

the second PPI devices each have a polygonal shape;

the second PPI devices each have a dimension that is no less than about 10 microns; and

each second PPI device is spaced apart from adjacent second PPI devices by a distance that is no less than about 10 microns.

7. The semieonductor device of claim 3, wherein:

the first PPI device includes a trench portion that is in direct contact with the first conductive pad; and

at least a subset of the second PPI devices include respective trench portions that are in direct contact with the respective second conductive pads.

8. The semiconductor device of claim. 3, further including:

a first polymer layer that is disposed. between the passivation layer and the first and second. PPI devices; and

a second polymer layer that is disposed over the first and second PPI devices.

9. A semiconductor device, comprising:

a plurality of functional conductive pads and a plurality of dummy conductive, pads formed over a substrate;

a passivation layer formed over the functional conductive pads and the dummy conductive pads, the passivation layer at least partially sealing the functional conductive pads and the dummy conductive pads;

a plurality of functional post-passivation interconnect (PPI) devices formed over the passivation layer, wherein each functional PPI devices is electrically coupled to a respective one of the functional conductive pads;

a plurality of dummy PPI devices formed over the passivation layer, wherein the dummy PPI devices are free of electrical coupling to the functional conductive pads;

a polymer layer fanned over the functional PPI devices and the dummy PPI devices; and

a plurality of conductive terminals formed over the polymer layer, wherein each of the conductive terminals is electrically coupled to at least one of the functional PPI devices, but the conductive terminals are free of electrical coupling to the dummy PPI devices.

10. The semiconductor device of claim 9, wherein:

the substrate includes a plurality of electronic components formed therein and an interconnect structure formed over the electronic components;

the functional conductive pads are each electrically coupled to at least one of the electronic components; and

the dummy conductive pads are free of electrical coupling to the electronic components.

11. The semiconductor device of claim 9, further including:

a plurality of functional conductive trenches that are each electrically coupled to a respective one of the functional PPI devices and a respective one of the functional conductive pads; and

a plurality of dummy conductive, trenches that are each electrically coupled to a respective one of the dummy PPI devices and a respective one of the dummy conductive pads.

12. The semiconductor device of claim 9, wherein:

the conductive terminals each include a solder ball;

the functional conductive pads and the dummy conductive pads include substantially identical material compositions; and

the functional PPI devices and the dummy PPI devices include substantially identical material compositions.

13. The semiconductor device of claim 9, wherein:

the dummy PPI devices each have a polygonal shape;

the dummy PPI devices each have a dimension that is greater than about 10 microns; and

each dummy PPI device is spaced apart from adjacent dummy PPI devices by a distance that is greater than about 10 microns.

14. A method, comprising:

forming a plurality of functional conductive pads and a plurality of dummy conductive pads over a wafer that contains an interconnect structure, wherein the functional conductive pads and the dummy conductive pads are formed over the interconnect structure;

forming a passivation layer over the functional conductive pads and the dummy conductive pads, the passivation layer at least partially sealing the functional conductive pads and the dummy conductive pads; and

forming a plurality of conductive terminals over the passivation layer, the conductive, terminals each being electrically coupled to at least one of the functional conductive pads but being free of electrical coupling to the dummy conductive pads; and

forming a pluralitv of functional post-passivation interconnect (PPI) devices, wherein the functional PPI devices are each electrically coupled to a respective one of the conductive terminals.

15. The method of claim 14, wherein:

the wafer contains a plurality of electronic components; and

the forming the functional conductive pads and the dummy conductive pads is carried out in a manner so that the functional conductive pads are each electrically coupled to at least one of the electronic components through the interconnect structure, and the dummy conductive pads are free of eletrical coupling to the electronic components,

16. The method of claim 14, further including, before the forming the conductive terminals:

forming plurality of dummy PPI devices over the passivation layer, wherein the dummy PPI devices are free of electrical coupling to the conductive terminals.

17. The method of claim 16, wherein:

the forming the functional PPI devices and the dummy PPI devices is carried out in a manner so that;

the functional PPI devices are each electrically coupled to a respective one of the functional conductive pads; and

the dummy PPI devices are free of electrical coupling to the functional conductive pads,

18. The method of claim 16, wherein:

the conductive terminal includes a solder ball;

the functional conductive pads and the dummy conductive pads have substantially identical material compositions; and

the functional PPI devices and the dummy PPI devices have substantially identical material compositions.

19. The method of claim 16, wherein the forming the dummy PPI devices, is carried out in a manner so that:

the dummy PPI devices each have a polygonal shape;

the dummy PPI devices each have a dimension that is no less than about 10 microns; and

each dummy PPI device is spaced apart from adjacent dummy PPI devices by a distance that is no less than about 10 microns.

20. The method of claim 16, wherein the forming the dummy PPI devices is carried out in a manner so that:

at least a subset of the dummy PPI devices include respective dummy trench portions that are in direct contact with the respective dummy conductive pads.