Voltage surge and overvoltage protection using prestored voltage-time profiles

• US 8,593,776 B2
• Filed: 11/16/2012
• Issued: 11/26/2013
• Est. Priority Date: 04/05/2007
• Status: Active Grant

• Current Assignee: I-EWM Acquisation, LLC
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Divan, Deepakraj M.
• Primary Examiner(s): Jackson, Stephen W
• Application Number:
  US13/679,705
• Publication Number:
  US 20130077198A1
• Time in Patent Office: 375 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H02H 3/207 also responsive to under-voltage window comparators for indication G01R19/165
• CPC Class Codes: H02H 9/002 limiting inrush current on switching on of inductive loads subjected to remanence, e.g. transformers
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/042 comprising means to limit the absorbed power or indicate damaged over-voltage protection device
• CPC Class Codes: H02H 9/044 Physical layout, materials not provided for elsewhere varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00

Abstract

Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.

Claims

1. A system, comprising:

at least one first voltage clamping device configured to clamp a voltage of an input power voltage applied to an electrical load;

at least one second voltage clamping device configured to clamp the voltage applied to the electrical load;

an inductance arranged between the first and second voltage clamping devices;

a switching element employed to selectively establish a coupling of the input power voltage to the electrical load; and

a processor circuit that controls the operation of the switching element, the processor circuit operative to;

store a plurality of predefined voltage-time thresholds in a memory;

monitor the input power voltage to identify an overvoltage experienced in the power voltage among the first clamping device and the second clamping device; and

time a duration of the overvoltage by controlling the switching element to selectively establish a coupling of the input power voltage to the electrical load such that, when the input power voltage experiences an overvoltage that extends beyond one or more of the voltage-time thresholds, the processor circuit manipulates the switching element to at least partially isolate the electrical load and the second voltage clamping device from the power voltage until the overvoltage has abated.

2. The system of claim 1, wherein the at least one first voltage clamping device comprises a metal-oxide varistor.

3. The system of claim 1, wherein a clamping voltage of the at least one first voltage clamping device is at least twice as high as a clamping voltage of the at least one second voltage clamping device.

4. The system of claim 1, wherein the switching element further comprises:

a first state in which the switching element establishes the coupling of the input power voltage to the electrical load; and

a second state in which the coupling is opened.

5. The system of claim 4, further comprising a series impedance coupled in parallel with the switching element, where the switching element presents a path of least resistance that bypasses the series impedance when the switching element is in the first state.

6. The system of claim 4, wherein the first switching element further couples a shunt resistance across the electrical load in the second state.

7. The system of claim 4, further comprising an impedance switching element configured to add an impedance to the electrical load, where the processor circuit further controls the operation of the impedance switching element.

8. A method, comprising the steps of:

applying an input power voltage to an electrical load;

distributing a dissipation of an overvoltage experienced in the input power voltage among a first clamping device and a second clamping device by arranging an inductance between the first and second clamping devices, the first and second clamping devices being arranged in parallel;

storing a plurality of predefined voltage-time thresholds in a memory;

monitoring the input power voltage to identify an overvoltage experienced in the input power voltage among the first clamping device and the second clamping device; and

timing a duration of the overvoltage by controlling a switching element to selectively establish a coupling of the input power voltage to the electrical load such that, when the input power voltage experiences an overvoltage that extends beyond one or more of the voltage-time thresholds, a processor circuit manipulates the switching element to at least partially isolate the electrical load and the second voltage clamping device from the input power voltage until the overvoltage has abated.

9. The method of claim 8, further comprising the step of switching an isolation relay from a first state to a second state, where the isolation relay couples the input power voltage to the electrical load in the first state, and the isolation relay imposes a shunt resistance across the electrical load in the second state.

10. The method of claim 9, further comprising the step of completely isolating the electrical load from the input power voltage when the isolation relay is in the second state.

11. The method of claim 9, wherein the electrical load is partially isolated from the input power voltage when the isolation relay is in the second state, where the isolation relay is coupled in parallel to an impedance.

12. The method of claim 8, further comprising the step of adding an impedance to the electrical load when the input power voltage experiences a voltage sag during a steady-state operation of the electrical load.

13. The method of claim 12, further comprising the step of removing the impedance from the electrical load when the input power voltage has reached a predefined point in the power voltage cycle after the input power voltage has returned to a nominal state.