Semiconductor integrated circuit deciding a power-supply voltage based on a delay test

• US 8,598,944 B2
• Filed: 07/24/2012
• Issued: 12/03/2013
• Est. Priority Date: 02/10/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fukuda, Nariyuki, Moriyasu, Noriyuki, Ooigawa, Isao, Furusawa, Toshiyuki, Kawakami, Satoko, Nemoto, Hitoshi, Fujioka, Hiroyuki, Sawada, Eiji, Tanaka, Tokio
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Kim, Jung H.
• Application Number:
  US13/556,364
• Publication Number:
  US 20130207692A1
• Time in Patent Office: 497 Days
• Field of Search: 327/530, 327/538, 327/540, 327/541, 327/543, 327/544, 327/545, 327/546, 713/320, 713/340
• US Class Current: 327/530
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Claims

1. A semiconductor integrated circuit, comprising:

a voltage regulator providing a prescribed power-supply voltage;

a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes;

a test control unit executing a delay test using the delay test circuit under a test mode while decreasing the power-supply voltage in a stepwise fashion;

a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test;

a memory unit storing the power-supply voltage of each operation mode;

a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

2. The semiconductor integrated circuit of claim 1, wherein

the power-supply voltage decision unit decides the lowest power-supply voltage as the power-supply voltage where all delay periods of the delay test circuits are set within a prescribed specification range.

3. The semiconductor integrated circuit of claim 2, wherein

the delay test circuit includes an equivalent critical pass circuit having delay characteristics corresponding to a critical pass.

4. The semiconductor integrated circuit of claim 3, wherein

the delay test circuit includes a delay circuit which adds a range of the delay period including non-uniformity of the delay characteristics to the equivalent critical pass circuit.

5. The semiconductor integrated circuit of claim 4, wherein

each of the delay test circuits includes scan flip-flops both at an input side and an output side.

6. The semiconductor integrated circuit of claim 5, wherein

both the scan flip-flops set in each input side of the delay test circuits and the scan flip-flops set in each output side of the delay test circuits are serially connected to constitute scan passes, respectively, and the test control unit sends test data for the delay test to the delay test circuit and receives output data from the delay test circuit through the scan pass.

7. The semiconductor integrated circuit of claim 3, wherein

the delay test is configured to execute after the semiconductor integrated circuit is mounted in equipment.

8. The semiconductor integrated circuit of claim 7, wherein

the memory unit includes a fuse ROM, the delay test is configured to execute when a shipment test is performed, and the power-supply voltage of the operation mode is written in the fuse ROM.

9. The semiconductor integrated circuit of claim 7, wherein

the memory unit reads out the power-supply voltage of the operation mode from the fuse ROM and the delay test is executed after the semiconductor integrated circuit is mounted in equipment.

10. The semiconductor integrated circuit of claim 4, wherein

the delay circuit is a variable delay circuit in which the delay period is configured to be shifted in stepwise fashion, the test control unit executes the delay test while shifting the delay period of the variable delay circuit, and output data of the delay test circuit outputted through the scan pass are outputted to an external terminal.

11. The semiconductor integrated circuit of claim 10, wherein

the variable delay circuit includes a plurality of unit variable delay circuits and a selector.

12. The semiconductor integrated circuit of claim 10, wherein

the unit variable delay circuits are serially connected and an output of each of the unit variable delay circuits is connected to an input of the selector.