Polyphase harmonic rejection mixer

• US 8,606,210 B2
• Filed: 02/03/2010
• Issued: 12/10/2013
• Est. Priority Date: 02/04/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Ru, Zhiyu, Klumperink, Eric A. M., Nauta, Bram, Brekelmans, Johannes H. A.
• Primary Examiner(s): PHU, SANH D
• Application Number:
  US13/147,779
• Publication Number:
  US 20110298521A1
• Time in Patent Office: 1,406 Days
• Field of Search: 455/323, 455/285, 455/302, 455/280, 455/284, 455/293
• US Class Current: 455/323
• CPC Class Codes: H03D 2200/0086 Reduction or prevention of harmonic frequencies
• CPC Class Codes: H03D 7/14 Balanced arrangements
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002

Abstract

A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Claims

1. A polyphase harmonic rejection mixer, comprising:

a plurality of stages following each other, the plurality of stages including;

a first stage configured and arranged to perform at least frequency conversion; and

a second stage configured and arranged to perform at least selective weighting and combining;

wherein at least two of the plurality of stages are configured and arranged to perform at least combining; and

further comprising at least one further stage, each said further stage being configured and arranged to perform selective weighting and combining

2. A polyphase harmonic rejection mixer according to claim 1, wherein the first stage is further configured and arranged to perform combining in addition to frequency conversion.

3. A polyphase harmonic rejection mixer according to claim 2, wherein the first stage is further configured and arranged to perform selective weighting in addition to frequency conversion and combining

4. A polyphase harmonic rejection mixer claim 1, wherein a following stage is configured and arranged to reduce a number of phases output by its preceding stage.

5. A polyphase harmonic rejection mixer according to claim 1, wherein a final stage is configured and arranged to output a complex differential down converted signal.

6. A polyphase harmonic rejection mixer according to claim 1, wherein the selective weighting in at least one of the stages is implemented by one of resistance, transconductance, and digital blocks.

7. A polyphase harmonic rejection mixer according to claim 6, wherein the selective weighting in at least one stage is implemented by plural gain blocks.

8. A polyphase harmonic rejection mixer according to claim 7, wherein the gain blocks are single-ended.

9. A polyphase harmonic rejection mixer according to claim 7, wherein each said gain block drives a respective set of plural mixers or samplers.

10. An LNA-less receiver comprising an antenna directly interfaced to a polyphase harmonic rejection mixer according to claim 1.

11. A software-defined radio comprising a polyphase harmonic rejection mixer according to claim 1.

12. A method of configuring a polyphase harmonic rejection mixer, the method comprising:

using a first stage of a plurality of stages, performing at least frequency conversion;

using a second stage of the plurality of stages, performing at least selective weighting and combining;

perform at least combining using at least two stages of the plurality of stages; and

using at least one further stage of the plurality of stages, performing selective weighting and combining.

13. The method according to claim 12, further comprising, using a following stage of the plurality of stages, reducing a number of phases output by a preceding one of the plurality of stages.

14. A polyphase harmonic rejection mixer, comprising a plurality of stages arranged in a pipeline and including:

a first stage configured and arranged to perform down conversion of an radio frequency (RF) signal to provide a first plurality of intermediate frequency (IF) signals having equidistant phases, the first plurality including a number (X) of IF signals;

a second stage coupled to an output of the first stage and configured and arranged to perform selective weighting of the first plurality of IF signals, and perform combining of the first plurality of IF signals to provide a second plurality of IF signals, the second plurality including a number (Y) of IF signals, where Y<

X; and

a third stage coupled to an output of the second stage and configured and arranged to perform selective weighting of the second plurality of IF signals, and perform combining of the second plurality of IF signals to provide a third plurality of IF signals, the third plurality including a number (Z) of IF signals, where Z<

Y.

15. A polyphase harmonic rejection mixer according to claim 14, wherein a final stage in the pipeline is configured and arranged to output a complex differential signal having four phases.

16. A polyphase harmonic rejection mixer according to claim 14, wherein:

the first plurality of IF signals includes 24 IF signals (X=24);

the second plurality of IF signals includes 8 IF signals (Y=8); and

the third plurality of IF signals includes 4 IF signals (Z=4).