Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer
First Claim
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1. A semiconductor device, comprising:
- a substrate having a gate trench;
a buried gate electrode partially filling the gate trench;
a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material layer that directly contacts an upper surface of the buried gate electrode;
a low-k material layer stacked over the first high-k material layer of the capping layer pattern;
source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode; and
a gate insulation layer interposed between the gate trench and the buried gate electrode and the low-k material layer and the source/drain regions.
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Abstract
Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.
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Citations
15 Claims
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1. A semiconductor device, comprising:
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a substrate having a gate trench; a buried gate electrode partially filling the gate trench; a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material layer that directly contacts an upper surface of the buried gate electrode; a low-k material layer stacked over the first high-k material layer of the capping layer pattern; source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode; and a gate insulation layer interposed between the gate trench and the buried gate electrode and the low-k material layer and the source/drain regions. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A dynamic random access memory (DRAM), comprising:
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an impurity layer in a substrate; a gate trench in the impurity layer and dividing the impurity layer into respectively separated source/drain regions; a buried gate electrode partially filling the gate trench; a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including, a bottom capping layer pattern and a top capping layer pattern, which are sequentially stacked, the bottom capping layer pattern including a first high-k material with a dielectric constant of more than 10, and the top capping layer pattern including a low-k material with a dielectric constant of less than 3; an interlayer insulation layer covering the capping layer pattern and the source/drain regions; and a storage electrode over the interlayer insulation layer and electrically connected to one of the source/drain regions. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device, comprising:
a buried channel array transistor (BCAT) formed within a substrate, the BCAT comprising, a gate electrode, a capping layer pattern over the gate electrode, the capping layer pattern including, a lower layer and an upper layer, the lower layer including a material with a dielectric constant of 10 or more, and the upper layer including a material with a dielectric constant of 3 or less, source/drain regions adjacent to sidewalls of the gate electrode, upper surfaces of the upper layer and of the source/drain regions being at the same height, and a gate insulation layer interposed between the substrate and the gate electrode. - View Dependent Claims (15)
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14. The semiconductor device of 13, wherein the gate insulation layer is further interposed between the upper layer and the source/drain regions.
Specification