Semiconductor device and semiconductor assembly with lead-free solder

• US 8,610,270 B2
• Filed: 02/09/2010
• Issued: 12/17/2013
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lai, Yi-Jen, Han, Chih-Kang, Chan, Chien-Pin, Chien, Chih-Yuan, Yang, Huai-Tei
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/702,636
• Publication Number:
  US 20110193219A1
• Time in Patent Office: 1,407 Days
• Field of Search: 257/737
• US Class Current: 257/738
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/1357 Single coating layer
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3651 : Formation of intermetallics

Abstract

A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a pad region on the semiconductor substrate;

a passivation layer over the semiconductor substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region; and

a bump structure overlying the pad region and electrically connected to the pad region via the opening;

wherein the bump structure comprises a copper layer and a SnAg layer overlying the copper layer, the SnAg layer has a melting temperature between 240°

C. and 280°

C., and the Ag content in the SnAg layer ranges from 1.2 weight percent to 1.6 weight percent.

2. The semiconductor device of claim 1, wherein the Ag content in the SnAg layer is 1.5 weight percent.

3. The semiconductor device of claim 1, wherein the copper layer is a copper post with a thickness greater than 40 um.

4. The semiconductor device of claim 1, wherein the copper layer has a thickness less than 10 um.

5. The semiconductor device of claim 1, further comprising a nickel layer between the copper layer and the SnAg layer.

6. The semiconductor device of claim 1, further comprising an under-bump metallization (UBM) layer between the bump structure and the pad region.

7. The semiconductor device of claim 1, further comprising a through via extending from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate and electrically connected to the pad region.

8. The semiconductor device of claim 1, wherein the through via comprises copper.

9. The semiconductor device of claim 1, further comprising an interconnect line between the bump structure and the pad region.

10. A semiconductor assembly comprising:

a first substrate;

a pad region over the first substrate;

a passivation layer over the first substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region;

a second substrate; and

a joint structure disposed between the first substrate and the second substrate and electrically connected to the pad region via the opening;

wherein the joint structure comprises a bump structure between the pad region of the first substrate and the second substrate and a solder layer between the bump structure and the second substrate;

wherein the solder layer comprises silver (Ag), and the Ag content in the solder layer is less than 3.0 weight percent; and

wherein at least one of the first substrate and the second substrate is a semiconductor substrate comprising a through via extending from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate and electrically connected to the bump structure.

11. The semiconductor assembly of claim 10, wherein the bump structure comprises a copper post with a thickness greater than 40 um.

12. The semiconductor assembly of claim 11, wherein the bump structure comprises a nickel-containing layer on the copper post.

13. The semiconductor assembly of claim 10, wherein the bump structure comprises has a copper layer with a thickness less than 10 um.

14. The semiconductor assembly of claim 13, wherein the bump structure comprises a nickel-containing layer on the copper layer.

15. The semiconductor assembly of claim 10, wherein each of the first substrate and the second substrate is a semiconductor substrate.

16. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate;

forming a pad region overlying the semiconductor substrate;

forming a passivation layer over the semiconductor substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region;

forming a copper post over the pad region, the copper post electrically connected to the pad region via the opening;

forming a lead-free solder layer over the copper post, wherein the lead-free solder layer comprises silver (Ag), the lead-free solder layer has a melting temperature between 240°

C. and 280°

C., and the Ag content in the lead-free solder layer is less than 1.6 weight percent; and

reflowing the lead-free solder layer.

17. The method of claim 16, wherein the Ag content in the lead-free solder layer is greater than 1.2 weight percent.

18. The method of claim 17, wherein the Ag content in the lead-free solder layer is 1.5 weight percent.

19. The method of claim 16, further comprising forming a nickel-containing layer over the copper post.