Method and system for managing a NAND flash memory by paging segments of a logical to physical address map to a non-volatile memory

• US 8,612,666 B2
• Filed: 06/30/2009
• Issued: 12/17/2013
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Royer, Robert J. Jr., Faber, Robert, Chartrand, Brent
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Gossage, Glenn
• Application Number:
  US12/495,573
• Publication Number:
  US 20100332730A1
• Time in Patent Office: 1,631 Days
• Field of Search: 711/103, 711/202, 711/206
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.

Claims

1. An apparatus coupled with a processor, comprising:

a NAND flash memory comprising a first memory;

a logical-to-physical (LTP) address mapping structure associated with the NAND flash memory, wherein the LTP address mapping structure includes a plurality of LTP entries each providing a logical address to a physical address mapping, wherein the LTP address mapping structure is divided into a plurality of segments;

a second memory storing information and instructions to be executed by the processor, wherein the second memory is operable to cache less than all the segments of the LTP address mapping structure;

a lookup table having a pointer for each segment of the LTP address mapping structure cached in the second memory and a physical address of each segment of the LTP address mapping structure in the first memory not cached in the second memory; and

logic coupled with the NAND flash memory to;

use the lookup table to control read and write to segments of the LTP address mapping structure in the NAND flash memory and to add and remove segments of the LTP address mapping structure in the second memory;

determine that one of the segments of the LTP address mapping structure not cached in the second memory comprises contiguous physical addresses for all entries in the determined segment not cached in the second memory, and

store in the lookup table a physical address corresponding to a first entry of a logical address of the determined one of the segments.

2. The apparatus of claim 1, wherein a size of each segment of the LTP address mapping structure is a page size of the NAND flash memory or a multiple of the page size.

3. The apparatus of claim 1, wherein the logic to control read and write to segments of the LTP address mapping structure is to further:

receive a request to write at least one of the segments to the NAND flash memory;

determine that an erase block of the NAND flash memory is available in response to receiving the request; and

write the at least one of the segments to the determined erase block.

4. The apparatus of claim 1, wherein the logic comprises a block storage driver.

5. The system of claim 1, wherein the logic further indicates the determined one of the segments as optimized.

6. A system including a processor comprising:

a NAND flash memory, comprising a first memory, to store a plurality of sections of an indirection system map of the NAND flash memory;

a second memory storing information and instructions executed by the processor, wherein the second memory is operable to cache less than all the sections of the indirection system map;

a lookup table indicating whether sections of the indirection system map are cached in the second memory or are stored in the NAND flash memory and indicating locations of the sections of the indirection system map in the second memory and the sections of the indirection system map in the NAND flash memory that are not cached in the second memory; and

logic to;

control caching of one or more of the plurality of sections of the indirection system map in the second memory;

determine that one of the sections of the indirection system map not cached in the second memory comprises contiguous physical addresses for all entries in the determined one of the sections not cached in the second memory, and

store in the lookup table a physical address corresponding to a first entry of a logical address of the determined one of the sections.

7. The system of claim 6, wherein the indirection system map comprises a logical-to-physical address mapping structure of the NAND flash memory.

8. The system of claim 6, wherein the logic further indicates the determined one of the sections as optimized.

9. The system of claim 6, wherein the logic is further to pin at least one of the cached one or more sections of the indirection system map in the second memory, wherein the pinned section is prevented from paging to the NAND flash memory.

10. The system of claim 6, wherein the second memory is one of Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS DRAM (RDRAM) and Double Data Rate three (DDR3) SDRAM.

11. The system of claim 6, wherein a size of each section of the indirection system map is a page size of the NAND flash memory or a multiple of the page size.

12. The system of claim 11, wherein the logic is to:

store a pointer in the lookup table to each section of the indirection system map cached in the second memory; and

store a physical page address in the lookup table of each section of the indirection system map not cached in the second memory.

13. The system of claim 6, wherein the logic is further to divide an unused portion of the second memory into a plurality of buffers, and to control caching of the one or more sections of the indirection system map into the plurality of buffers.

14. The system of claim 13, wherein the logic is further to:

determine that the lookup table is to indicate that a section of the indirection system map to be accessed is not cached in the second memory;

determine whether at least one of the buffers in the second memory is unused;

cache the section of the indirection system map to be accessed from the NAND flash memory into the at least one unused buffer in the second memory in response to determining that there is at least one unused buffer in the second memory;

select one or more sections of the indirection system map cached in one or more of the buffers to be evicted to the NAND flash memory based on a caching policy in response to determining that there are no unused buffers in the second memory;

evict the selected one or more sections of the indirection system map to the NAND flash memory; and

cache the section of the indirection system map to be accessed from the NAND flash memory into the one or more of the buffers of the second memory.

15. A method comprising:

partitioning a logical-to-physical (LTP) indirection map of a non-volatile memory into a plurality of segments, wherein the LTP indirection map includes a plurality of LTP entries each providing a logical address to a physical address mapping, wherein each of the segments includes a plurality of LTP entries;

storing a lookup table having a pointer for each segment of the LTP indirection map cached in a volatile memory and a physical address of each segment of the LTP indirection map in the non-volatile memory not cached in the volatile memory; and

paging the segments of the LTP indirection map to the non-volatile memory, wherein the segments of the LTP indirection map are capable of being stored in non-contiguous locations in the non-volatile memory;

determining that one of the segments of the LTP indirection map not cached in the volatile memory comprises contiguous physical addresses for all entries in the determined segment not cached in the volatile memory, and

storing in the lookup table a physical address corresponding to a first entry of a logical address of the determined one of the segments.

16. The method of claim 15, wherein partitioning the LTP indirection map of the non-volatile memory into the plurality of segments comprises partitioning the LTP indirection map of the non-volatile memory into a plurality of page-sized segments.

17. The method of claim 15, wherein the non-volatile memory is a NAND flash memory, and wherein paging of the segments of the LTP indirection map to the NAND flash memory comprises:

determining that an erase block of the NAND flash memory does not contain any user data; and

writing at least one of the segments of the LTP indirection map to the determined erase block.

18. The method of claim 15, the method further comprising:

receiving a notification of power failure of the non-volatile memory;

determining that a size of the LTP indirection map is less than an unutilized memory space in a second memory in response to receiving the notification;

building another LTP indirection map in the unutilized memory space in the second memory; and

paging the another LTP indirection map to the non-volatile memory.

19. The method of claim 15, further comprising indicating the determined one of the segments as optimized.

20. The method of claim 15, further comprising maintaining a segment table associated with the LTP indirection map, wherein the segment table is to specify where each segment of the LTP indirection map is located.

21. The method of claim 20, wherein the non-volatile memory is a NAND flash memory, further comprising:

receiving a notification of power failure of the non-volatile memory;

determining that a size of the LTP indirection map is more than an unutilized memory space in a memory in response to receiving the notification;

identifying at least one erase block of the NAND flash memory storing the segments of the LTP indirection map; and

building the segment table using the stored segments of the LTP indirection map in the identified at least one erase block.