Power detector radio frequency multiplexer

• US 8,619,639 B2
• Filed: 07/06/2007
• Issued: 12/31/2013
• Est. Priority Date: 07/06/2007
• Status: Expired due to Fees

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Lantiq Deutschland GMBH (Intel Corporation)
• Inventors: Mertens, Koen, Wiesbauer, Andreas, Derksen, Sven, Tiebout, Marc
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US11/774,432
• Publication Number:
  US 20090011734A1
• Time in Patent Office: 2,370 Days
• Field of Search: None
• US Class Current: 370/277
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control

Abstract

A disclosed circuit arrangement may include a power detector. A multiplexer circuit may be coupled to the power detector. The multiplexer circuit may include at least two switching sections, one of the switching sections to pass a radio frequency (RF) signal generated based on a first modulation scheme to the power detector and another of the switching sections to pass an RF signal generated based on a second modulation scheme to the power detector.

Claims

1. A circuit arrangement, comprising:

a power detector; and

a multiplexer circuit coupled to the power detector, the multiplexer circuit including at least two switching sections, one of the switching sections to pass a radio frequency (RF) signal generated based on a first modulation scheme to the power detector and another of the switching sections to pass an RF signal generated based on a second modulation scheme to the power detector, wherein the power detector is common to the at least two switching sections.

2. The circuit according to claim 1, wherein each of the at least two switching sections includes a switch that enables RF signals to pass to the power detector, the switch of each of the at least two switching sections to pass RF signals to the power detector when in a closed state.

3. The circuit according to claim 2, wherein the switch of each of the at least two switching sections prevents RF signals to pass to the power detector when in an open state.

4. The circuit according to claim 1, wherein each of the at least two switching sections includes a switch that enables RF signals to pass to ground, the switch of each of the at least two switching sections to pass RF signals to ground when in a closed state.

5. The circuit according to claim 4, wherein the switch of each of the at least two switching sections prevents RF signals to pass to ground when in an open state.

6. The circuit according to claim 1, wherein each of the at least two switching sections includes a switch that enables RF signals to pass to the power detector and another switch that enables RF signals to pass to ground, the switches of each of the at least two switching sections toggled oppositely when the multiplexer circuit is actively processing any RF signal.

7. The circuit according to claim 1, wherein each of the at least two switching sections includes two switches in parallel, one of the switches coupled to ground and another of the switches coupled to an input of the power detector.

8. The circuit according to claim 7, wherein each of the at least two switching sections includes a capacitor, each capacitor of the at least two switching sections coupled to the at least two switches of a respective one of the at least two switching sections.

9. A circuit arrangement, comprising:

a power detector; and

a multiplexer circuit coupled to the power detector, the multiplexer circuit including at least four switching sections, two of the switching sections to pass differential radio frequency (RF) signals generated based on a first modulation scheme to the power detector and another two of the switching sections to pass differential RF signals generated based on a second modulation scheme to the power detector.

10. The circuit according to claim 9, wherein each of the at least four switching sections includes a switch that enables RF signals to pass to the power detector, the switch of each of the at least four switching sections to pass RF signals to the power detector when in a closed state.

11. The circuit according to claim 10, wherein the switch of each of the at least four switching sections prevents RF signals to pass to the power detector when in an open state.

12. The circuit according to claim 9, wherein each of the at least four switching sections includes a switch that enables RF signals to pass to ground, the switch of each of the at least four switching sections to pass RF signals to ground when in a closed state.

13. The circuit according to claim 12, wherein the switch of each of the at least four switching sections prevents RF signals to pass to ground when in an open state.

14. The circuit according to claim 9, wherein each of the at least four switching sections includes two switches in parallel, one of the switches coupled to ground and another of the switches coupled to an input of the power detector.

15. A wireless system, comprising:

an integrated circuit having a multiplexer circuit, the multiplexer circuit including at least two switching sections, one of the switching sections to pass a radio frequency (RF) signal generated based on a first modulation scheme and another of the switching sections to pass an RF signal generated based on a second modulation scheme,

wherein the multiplexer circuit of the integrated circuit is coupled to a single power detector.

16. A method, comprising:

receiving at least two radio frequency (RF) signals, one of the at least two received RF signals generated based on a first modulation scheme and another of the at least two received RF signals generated based on a second modulation scheme;

processing the at least two RF signals by way of a multiplexer circuit, the multiplexer circuit including at least two switching sections, one of the switching sections to pass RF signals generated based on a first modulation scheme and another of the switching sections to pass RF signals generated based on a second modulation scheme; and

detecting signal attributes associated with each of the at least two RF signals by way of a common power detector.

17. The method according to claim 16, wherein the received at least two RF signals include differential RF signals.

18. The method according to claim 16, wherein each of the at least two switching sections of the multiplexer circuit includes a switch that enables RF signals to pass to the common power detector, the switch of each of the at least two switching sections to pass RF signals to the common power detector when in a closed state.

19. A circuit arrangement, comprising:

a power detector; and

a multiplexer circuit coupled to the power detector, the multiplexer circuit including at least two switching sections, one of the switching sections to pass a radio frequency (RF) signal generated based on a first modulation scheme to the power detector and another of the switching sections to pass a reference signal.

20. The circuit arrangement according to claim 19, wherein the circuit arrangement is employed in an ultra wideband system.

21. A circuit arrangement, comprising:

a power detector; and

a multiplexer circuit coupled to the power detector, the multiplexer circuit including at least two switching sections, one of the switching sections to pass a signal generated based on a modulation scheme to the power detector and another of the switching sections to pass a signal to calibrate the power detector.

22. The circuit according to claim 21, wherein each of the at least two switching sections includes a switch that enables signals to pass to the power detector, the switch of each of the at least two switching sections to pass signals to the power detector when in a closed state.

23. The circuit according to claim 22, wherein the switch of each of the at least two switching sections prevents signals to pass to the power detector when in an open state.

24. The circuit according to claim 21, wherein each of the at least two switching sections includes a switch that enables signals to pass to ground, the switch of each of the at least two switching sections to pass signals to ground when in a closed state.

25. The circuit according to claim 23, wherein the switch of each of the at least two switching sections prevents signals to pass to ground when in an open state.

26. The circuit according to claim 21, wherein each of the at least two switching sections includes a switch that enables signals to pass to the power detector and another switch that enables signals to pass to ground, the switches of each of the at least two switching sections toggled oppositely when the multiplexer circuit is actively processing any signal.

27. The circuit according to claim 21, wherein each of the at least two switching sections including two switches in parallel, one of the switches coupled to ground and another of the switches coupled to an input of the power detector.

28. The circuit according to claim 27, wherein each of the at least two switching sections includes a capacitor, each capacitor of the at least two switching sections coupled to the at least two switches of a respective one of the at least two switching sections.

29. A wireless system, comprising:

an integrated circuit having a multiplexer circuit, the multiplexer circuit including at least two switching sections, one of the switching sections to pass a signal generated based on a modulation scheme and another of the switching sections to pass a calibration signal,

wherein the multiplexer circuit of the integrated circuit is coupled to a single power detector.

30. The wireless system according to claim 29, wherein the multiplexer circuit of the integrated circuit is coupled to a single power detector.

31. The wireless system according to claim 30, wherein the calibration signal is to calibrate the single power detector.