Nano-sense amplifier
First Claim
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1. A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including:
- a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, anda reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter,wherein one or more of the transistors are multigate transistors.
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Abstract
A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.
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20 Claims
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1. A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including:
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a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter, wherein one or more of the transistors are multigate transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 20)
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13. A sense amplifier (nSA) including:
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a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local line, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter; wherein one or more transistors of the writing stage and of the reading stage are independent double gate transistors.
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19. A matrix array of cells comprising sense amplifiers and column decoders, wherein the sense amplifiers are arranged in a non-staggered fashion in one or more sense amplifier banks and wherein a column decoder is placed next to each bank and configured to drive said bank directly.
Specification