High speed processing of financial information using FPGA devices

  • US 8,626,624 B2
  • Filed: 03/31/2011
  • Issued: 01/07/2014
  • Est. Priority Date: 06/19/2006
  • Status: Active Grant
First Claim
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1. An apparatus for processing financial market data messages, the messages having a message format and comprising a plurality of data fields, each data field having a data value, the apparatus comprising:

  • a reconfigurable logic device; and

    a memory configured to store a data dictionary, the data dictionary comprising a plurality of entries corresponding to the message format, the entries configured to describe (1) a plurality of fields for the message format, (2) a plurality of positions for the fields within the financial market data messages having the message format, (3) a plurality of sizes for the fields within the financial market data messages having the message format, and (4) metadata for the fields within the financial market data messages having the message format; and

    wherein the reconfigurable logic device comprises firmware logic, the firmware logic configured to (1) access the memory to read the data dictionary entries, and (2) parse a plurality of financial market data messages having the message format into their constituent data fields in accordance with the data dictionary entries to thereby generate a stream of parsed financial market data, the parsed financial market data comprising a plurality of data values for a plurality of the data fields and metadata from the data dictionary entries corresponding to the data fields; and

    wherein the reconfigurable logic device and the memory are configured to support parsing of different message formats without altering the firmware logic by changing the data dictionary entries to be accessed and read by the firmware logic.

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