Three dimensional structure memory

• US 8,629,542 B2
• Filed: 03/17/2009
• Issued: 01/14/2014
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US12/405,234
• Publication Number:
  US 20090174082A1
• Time in Patent Office: 1,764 Days
• Field of Search: 257/777, 257/778, 257/E21.597, 438/455, 438/598
• US Class Current: 257/686
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit comprising:

a circuit substrate;

a first integrated circuit having circuitry formed on a front surface thereof, the front surface or a back surface being bonded to the circuit substrate; and

one or more additional integrated circuits each having circuitry formed on respective front surfaces thereof, each additional integrated circuit having the front surface or a back surface thereof adjacent to the front surface or a back surface of an adjacent integrated circuit;

wherein at least one of the first integrated circuit and the one or more additional integrated circuits is substantially flexible and comprises a substantially flexible semiconductor substrate of one piece made from a semiconductor wafer thinned by at least one of abrasion, etching and parting, and subsequently polished to form a polished surface.

2. The stacked integrated circuit of claim 1, wherein at least one of the integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm² tensile or less.

3. The stacked integrated circuit of claim 2, wherein the at least one of the first integrated circuit and the one or more additional integrated circuits comprises integrated circuitry defining an integrated circuit die having an area, wherein the substrate of the at least one of the first integrated circuit and the one or more additional integrated circuits extends throughout at least a substantial portion of the area of the integrated circuit die.

4. The stacked integrated circuit of claim 3, wherein the circuit substrate is an integrated circuit substrate having circuitry formed on a front surface thereof wherein the front surfaces of the integrated circuit substrate and the first integrated circuit are bonded together.

5. The stacked integrated circuit of claim 4, further comprising a thermal diffusion bond joining the integrated circuit substrate and the first integrated circuit.

6. The stacked integrated circuit of claim 4, further comprising thermal diffusion bonds joining each additional integrated circuit to an adjacent integrated circuit.

7. The stacked integrated circuit of claim 3, further comprising a second integrated circuit and vertical interconnects connecting circuitry of the first integrated circuit and circuitry of the second integrated circuit, wherein a plurality of interconnects are closely arrayed to form a group of interconnects.

8. The stacked integrated circuit of claim 7, wherein a group of interconnects extends continuously between multiple integrated circuits.

9. The stacked integrated circuit of claim 7, wherein the interconnects are formed at least in part by a thermal diffusion bond.

10. The stacked integrated circuit of claim 3, wherein the first integrated circuit and the additional integrated circuit are formed with one of single crystal semiconductor material and polysilicon semiconductor material.

11. The stacked integrated circuit of claim 3, further comprising a second integrated circuit, wherein one of the first and additional integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

12. The stacked integrated circuit of claim 3, wherein at least one of the first and additional integrated circuits comprises a microprocessor.

13. The stacked integrated circuit of claim 3, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

14. The stacked integrated circuit of claim 3, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

15. The stacked integrated circuit of claim 3, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

16. The stacked integrated circuit of claim 3, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.

17. The stacked integrated circuit of claim 3, further comprising a second integrated circuit, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuits.

18. The stacked integrated circuit of claim 3, further comprising a second integrated circuit, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

19. The stacked integrated circuit of claim 3, wherein at least one integrated circuit has reconfiguration circuitry.

20. The stacked integrated circuit of claim 3, further comprising at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

21. The stacked integrated circuit of claim 3, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

22. The stacked integrated circuit of claim 3, further comprising:

one or more controller integrated circuits;

one or more memory integrated circuits;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering in at least one instance said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

23. The stacked integrated circuit of claim 22, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

24. The stacked integrated circuit of claim 22, further comprising programmable logic to prevent the use of data values from data lines when gate lines ′

cause said detected defective memory cells to couple data values to said data lines.

25. The stacked integrated circuit of claim 22, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

26. The stacked integrated circuit of claim 22, wherein external testing of the controller logic together with testing by the controller logic of the memory cells achieves a functional testing of a preponderance of the memory cells.

27. The stacked integrated circuit of claim 22, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

28. The stacked integrated circuit of claim 22 wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

29. The stacked integrated circuit of claim 3, wherein the first integrated circuit is fabricated using one process technology, and the one or more additional integrated circuits are fabricated using a different process technology.

30. The stacked integrated circuit of claim 3, wherein at least one of the integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.

31. The stacked integrated circuit of claim 3, wherein the first integrated circuit is formed on a monocrystalline semiconductor substrate.

32. The apparatus of claim 3, wherein at least one conductive path pass through the monocrystalline semiconductor substrate and is insulated by an insulation material from said monocrystalline semiconductor substrate.

33. The stacked integrated circuit of claim 3, wherein a back surface of the first integrated circuit is polished.

34. The stacked integrated circuit of claim 3, further comprising a second integrated circuit and vertical interconnects connecting at least two of said circuit substrate, said first integrated circuit, and said second integrated circuit, wherein each of said vertical interconnects comprises a conductive center portion and an insulating portion surrounding the conductive center portion.

35. The stacked integrated circuit of claim 34, wherein the insulating portion surrounding the conductive center portion of said vertical interconnects comprises a dielectric material having a stress of 5×

10⁸ dynes/cm² tensile or less.

36. The stacked integrated circuit of claim 34, wherein at least one of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnects comprises a dielectric material having a stress of 5×

10⁸ dynes/cm² tensile or less;

one of the first integrated circuit and the one or more additional integrated circuits is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of the first integrated circuit and the one or more additional integrated circuits comprises a microprocessor;

the first integrated circuit and the one or more additional integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the integrated circuits;

continuous vertical interconnections connect circuitry of the first and second integrated circuits;

information processing is performed on data routed between circuitry on the first and second integrated circuits;

at least one integrated circuit has reconfiguration circuitry;

vertical interconnects connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric having stress of 5×

10⁸ dynes/cm² tensile or less;

at least one of the circuit substrate and the first integrated circuit is substantially flexible;

at least one of the circuit substrate and the first integrated circuit comprises a dielectric layer with a stress of about 5×

10⁸ dynes/cm² tensile or less;

the first integrated circuit and the one or more additional integrated circuits form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks are configured to independently perform memory operations;

a plurality of vertical interconnects are provided each of which extends through one of a plurality of holes in semiconductor material of the substantially flexible semiconductor substrate from a first surface of the substantially flexible semiconductor substrate to an opposite surface thereof and comprises a conductive center portion and a silicon-based dielectric insulating portion surrounding the conductive center portion;

a plurality of polysilicon substrates and a plurality of low stress silicon-based dielectric layers are arranged in a stacked relationship to at least one of the first integrated circuit and the one or more additional integrated circuits;

at least one of the first integrated circuit and the at one or more additional integrated circuits comprises a front surface and a back surface opposite the front surface, further comprising a tensile low stress silicon-based dielectric material with a stress of about 5×

10⁸ dynes/cm² tensile or less on the back surface.

37. The stacked integrated circuit of claim 34, wherein at least two of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnects comprises a dielectric material having a stress of 5×

10⁸ dynes/cm² tensile or less;

one of the first integrated circuit and the one or more additional integrated circuits is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of the first integrated circuit and the one or more additional integrated circuits comprises a microprocessor;

the first integrated circuit and the one or more additional integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the integrated circuits;

continuous vertical interconnections connect circuitry of the first and second integrated circuits;

information processing is performed on data routed between circuitry on the first and second integrated circuits;

at least one integrated circuit has reconfiguration circuitry;

vertical interconnects connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric having stress of 5×

10⁸ dynes/cm² tensile or less;

at least one of the circuit substrate and the first integrated circuit is substantially flexible;

at least one of the circuit substrate and the first integrated circuit comprises a dielectric layer with a stress of about 5×

10⁸ dynes/cm² tensile or less the first integrated circuit and the one or more additional integrated circuits form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks are configured to independently perform memory operations;

a plurality of vertical interconnects are provided each of which extends through one of a plurality of holes in semiconductor material of the substantially flexible semiconductor substrate from a first surface of the substantially flexible semiconductor substrate to an opposite surface thereof and comprises a conductive center portion and a silicon-based dielectric insulating portion surrounding the conductive center portion;

a plurality of polysilicon substrates and a plurality of low stress silicon-based dielectric layers are arranged in a stacked relationship to at least one of the first integrated circuit and the one or more additional integrated circuits;

at least one of the first integrated circuit and the at one or more additional integrated circuits comprises a front surface and a back surface opposite the front surface, further comprising a tensile low stress silicon-based dielectric material with a stress of about 5×

10⁸ dynes/cm² tensile or less on the back surface;

a plurality of processing technologies are used to fabricate the first integrated circuit and the one or more additional integrated circuits of the stacked integrated circuit.

38. The stacked integrated circuit of claim 34, wherein at least three of the following:

the insulating portion surrounding the conductive center portion of said vertical interconnects comprises a dielectric material having a stress of 5×

10⁸ dynes/cm² tensile or less;

one of the first integrated circuit and the one or more additional integrated circuits is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of the first integrated circuit and the one or more additional integrated circuits comprises a microprocessor;

the first integrated circuit and the one or more additional integrated circuits comprise at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit;

a plurality of interior vertical interconnections traverse at least one of the integrated circuits;

continuous vertical interconnections connect circuitry, of the first and second integrated circuits;

information processing is performed on data routed between circuitry on the first and second integrated circuits;

at least one integrated circuit has reconfiguration circuitry;

vertical interconnects connect the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric having stress of 5×

10⁸ dynes/cm² tensile or less;

at least one of the circuit substrate and the first integrated circuit is substantially flexible;

at least one of the circuit substrate and the first integrated circuit comprises a dielectric layer with a stress of about 5×

10⁸ dynes/cm² tensile or less the first integrated circuit and the one or more additional integrated circuits form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks are configured to independently perform memory operations;

a plurality of vertical interconnects are provided each of which extends through one of a plurality of holes in semiconductor material of the substantially flexible semiconductor substrate from a first surface of the substantially flexible semiconductor substrate to an opposite surface thereof and comprises a conductive center portion and a silicon-based dielectric insulating portion surrounding the conductive center portion;

a plurality of polysilicon substrates and a plurality of low stress silicon-based dielectric layers are arranged in a stacked relationship to at least one of the first integrated circuit and the one or more additional integrated circuits;

at least one of the first integrated circuit and the at one or more additional integrated circuits comprises a front surface and a back surface opposite the front surface, further comprising a tensile low stress silicon-based dielectric material with a stress of about 5×

10⁸ dynes/cm² tensile or less on the back surface;

a plurality of processing technologies are used to fabricate the first integrated circuit and the one or more additional integrated circuits of the stacked integrated circuit.

39. The stacked integrated circuit of claim 3, further comprising vertical interconnects connecting the circuit substrate and circuitry of the first integrated circuit, each vertical interconnect comprising a conductive center portion and a insulating portion surrounding the conductive center portion, the insulating portion comprising a dielectric having stress of 5×

10⁸ dynes/cm² tensile or less.

40. The stacked integrated circuit of claim 3, wherein at least one of the circuit substrate and the first integrated circuit is substantially flexible.

41. The stacked integrated circuit of claim 40, wherein the at least one of the circuit substrate and the first integrated circuit comprises a dielectric layer with a stress of about 5×

10⁸ dynes/cm² tensile or less.

42. The stacked integrated circuit of claim 3, wherein the substantially flexible semiconductor substrate is one thinned by parting the semiconductor substrate at a parting layer comprising implanted hydrogen species.

43. The stacked integrated circuit of claim 1, wherein the first integrated circuit and the one or more additional integrated circuits form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks are con figured to independently perform memory operations.

44. The stacked integrated circuit of claim 1, comprising:

a plurality of vertical interconnects each of which extends through one of a plurality of holes in semiconductor material of the substantially flexible semiconductor substrate from a first surface of the substantially flexible semiconductor substrate to an opposite surface thereof and comprises a conductive center portion and a silicon-based dielectric insulating portion surrounding the conductive center portion.

45. The stacked integrated circuit of claim 1, further comprising a plurality of polysilicon substrates and a plurality of low stress silicon-based dielectric layers in a stacked relationship to at least one of the first integrated circuit and the one or more additional integrated circuits.

46. The stacked integrated circuit of claim 1, wherein at least one of the first integrated circuit and the at one or more additional integrated circuits comprises a front surface and a back surface opposite the front surface, further comprising a tensile low stress silicon-based dielectric material with a stress of about 5×

10⁸ dynes/cm² tensile or less on the back surface.

47. The stacked integrated circuit of claim 1, wherein a plurality of processing technologies are used to fabricate the first integrated circuit and the one or more additional integrated circuits of the stacked integrated circuit.

48. The stacked integrated circuit of claim 1, wherein at least one of the first integrated circuit and the one or more additional integrated circuits comprises a first side and a second side opposite the first side, further comprising integrated circuitry formed on the first side and interconnections for at least a portion of the integrated circuitry formed on the second side.

49. The stacked integrated circuit of claim 4, wherein the circuit substrate, the first integrated circuit and the one or more additional integrated circuits form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks are configured to independently perform memory operations.