RFID transponder with PLL

• US 8,629,759 B2
• Filed: 08/28/2008
• Issued: 01/14/2014
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.)
• Inventors: Muellner, Ernst
• Primary Examiner(s): Bugg, George
• Assistant Examiner(s): Afrifa-Kyei, Anthony D
• Application Number:
  US12/200,521
• Publication Number:
  US 20090174592A1
• Time in Patent Office: 1,965 Days
• Field of Search: 340/10.1
• US Class Current: 340/10.1
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H04B 1/00 Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission

Abstract

An RFID transponder comprises an antenna for receiving data in a downlink mode and transmitting data in an uplink mode, with a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data. A class C amplifier is provided, which has a resonant circuit, a plucking device coupled to the resonant circuit, and a controllable pulse width generator coupled to the plucking device. The controllable pulse width generator is adapted to periodically switch the plucking device on and off so as to maintain an oscillation of the resonant circuit. The transponder further comprises a phase locked loop configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an independent internal clock signal for the RFID transponder.

Claims

1. An RFID transponder, comprising:

an antenna for receiving data in a downlink mode and transmitting data in an uplink mode;

a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data; and

a class C amplifier comprising a resonant circuit (L, C), a plucking device (T1) coupled to the resonant circuit, and a controllable pulse width generator (PWM) coupled to the plucking device (T1), the controllable pulse width generator (PWM) being adapted to periodically switch the plucking device (T1) on and off so as to maintain an oscillation of the resonant circuit (L, C), wherein the transponder further comprises a phase locked loop (PLL) configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an internal clock signal for the RFID transponder, which is independent from the oscillating signal received through the antenna;

an end of burst stage (EOB) for detecting an end of a burst of downlink data and being adapted to signal to the phase locked loop (PLL), upon detection of the end of the burst of downlink data, that the phase locked loop (PLL) is to be set into free running mode, so as to maintain the oscillating frequency without an external reference, wherein the end of burst stage (EOB) is further adapted to detect whether an amplitude of an uplink signal is greater than a predetermined level and to provide a control signal for the class C amplifier to reduce the pulse width of the pulse width modulated signal from the pulse width modulator (PWM) upon detection that the amplitude of the uplink signal is greater than said predetermined level.

2. The RFID transponder according to claim 1, wherein the modulation stage comprises means (MODCAP) for tuning an oscillating frequency of the resonant circuit (L, C) to provide an uplink FSK signal, the RFID transponder being adapted to change an oscillating frequency of the phase locked loop (PLL) in accordance with a change of the oscillating frequency of the resonant circuit (L, C).

3. The RFID transponder according to claim 1, further comprising a multiplexer (MUX) adapted to switch the internal clock signal between the clock signal output by the phase locked loop (PLL) and a test clock signal externally applied to the transponder.

4. The RFID transponder according to claim 2, further comprising a multiplexer (MUX) adapted to switch the internal clock signal between the clock signal output by the phase locked loop (PLL) and a test clock signal externally applied to the transponder.

5. A method for operating a RFID transponder, which is adapted to receive data in a downlink mode and to transmit data in an uplink mode, the method comprising:

locking a phase locked loop (PLL) to an oscillating signal received through an antenna; and

switching the phase locked loop (PLL) into a free running mode without being locked to the oscillating signal received through the antenna thereby providing an internal clock signal for the RFID transponder at an output of the phase locked loop (PLL), which is independent from the oscillating signal received through the antenna; and

detecting in an end of burst stage (EOB) an end of a burst of downlink data and signalling to the phase locked loop (PLL), upon detection of the end of the burst of downlink data, that the phase locked loop (PLL) is to be set into free running mode, so as to maintain the oscillating frequency without an external reference, wherein the end of burst stage (EOB) detects whether an amplitude of an uplink signal is greater than a predetermined level and to provide a control signal for the class C amplifier to reduce the pulse width of the pulse width modulated signal from the pulse width modulator (PWM) upon detection that the amplitude of the uplink signal is greater than said predetermined level.

6. In an RFID transponder, having an antenna for receiving data in a downlink mode and transmitting data in an uplink mode and a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data;

an oscillator comprising;

a class C amplifier comprising a resonant circuit (L, C), a plucking device (T1) coupled to the resonant circuit, and a controllable pulse width generator (PWM) coupled to the plucking device (T1), the controllable pulse width generator (PWM) being adapted to periodically switch the plucking device (T1) on and off so as to maintain an oscillation of the resonant circuit (L, C); and

an end of burst stage (EOB) for detecting an end of a burst of downlink data and being adapted to signal to the phase locked loop (PLL), upon detection of the end of the burst of downlink data, that the phase locked loop (PLL) is to be set into free running mode, so as to maintain the oscillating frequency without an external reference, wherein the end of burst stage (EOB) is further adapted to detect whether an amplitude of an uplink signal is greater than a predetermined level and to provide a control signal for the class C amplifier to reduce the pulse width of the pulse width modulated signal from the pulse width modulator (PWM) upon detection that the amplitude of the uplink signal is greater than said predetermined level.