Enhanced multi-processor waveform data exchange using compression and decompression

• US 8,631,055 B2
• Filed: 09/27/2010
• Issued: 01/14/2014
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Samplify Systems Incorporated
• Inventors: Wegener, Albert W.
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US12/891,312
• Publication Number:
  US 20110078222A1
• Time in Patent Office: 1,205 Days
• Field of Search: None
• US Class Current: 708/203
• CPC Class Codes: H03M 7/24 Conversion to or from floating-point codes
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
• CPC Class Codes: H03M 7/3059 Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
• CPC Class Codes: H03M 7/6023 Parallelization
• CPC Class Codes: H03M 7/6064 Selection of Compressor

Abstract

Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data. This abstract does not limit the scope of the invention as described in the claims.

Claims

1. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for compressing waveform data for storage in the second memory device, comprising:

receiving a request at the memory controller from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format;

receiving one or more compression control parameters from the processor at compression logic integrated with the memory controller;

receiving the plurality of samples at the compression logic in the memory controller from the first memory device in response to the request from the processor;

the compression logic compressing the plurality of samples in accordance with the compression control parameter to form a plurality of compressed samples for a compressed packet; and

transferring the compressed packet to the second memory device, the second memory device storing the compressed packet,

wherein a first one of the compression control parameters is a data type parameter of the samples, the data type parameter indicating the integer data format or the floating-point data format, wherein for the integer data format, each input sample consists of a first sign bit and a first plurality of mantissa bits and for the floating-point data format, each sample consists of a second sign bit, a second plurality of mantissa bits and a plurality of floating-point exponent bits, the method further comprising;

configuring said compressing to process the first sign bit and the first plurality of mantissa bits of each sample when the data type parameter indicates the integer data format; and

configuring said compressing to process the second sign bit, the second plurality of mantissa bits and the plurality of floating-point exponent bits of each sample when the data type parameter indicates the floating-point data format.

2. The method of claim 1, wherein one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said compressing applies lossless compression operations or lossy compression operations to the samples in accordance with the compression mode parameter.

3. The method of claim 1, wherein one of the compression control parameters is a desired number of bits per compressed packet or a desired compression ratio.

4. The method of claim 1, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the integer data format, said compressing further comprising:

applying lossless compression operations or lossy compression operations to the first sign bit and the first plurality of mantissa bits of each sample in accordance with the compression mode parameter.

5. The method of claim 1, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the floating-point data format, said compressing further comprising:

separating the plurality floating-point exponent bits from the second sign bit and the second plurality of mantissa bits of each sample;

applying lossless compression operations to the plurality of floating-point exponent bits of each sample to produce a plurality of compressed floating-point exponents;

applying lossless compression operations or lossy compression operations to the second sign bit and the second plurality of mantissa bits of each sample in accordance with the compression mode parameter to form a plurality of compressed signs and mantissas; and

providing the plurality of compressed floating-point exponents and the plurality of compressed signs and mantissas to the compressed packet.

6. The method of claim 1, wherein the system includes a plurality of processors integrated on the chip, the memory controller receiving requests form one or more of the processors to write respective waveform data to the second memory device, said compressing applied to respective pluralities of samples to form respective pluralities of compressed samples.

7. The method of claim 1, wherein the memory controller further comprises a direct memory access controller, wherein the compression logic is integrated with the direct memory access controller to perform said compressing.

8. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for compressing waveform data for storage in the second memory device, comprising:

receiving a request at the memory controller from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format;

receiving one or more compression control parameters from the processor at compression logic integrated with the memory controller;

receiving the plurality of samples at the compression logic in the memory controller from the first memory device in response to the request from the processor;

the compression logic compressing the plurality of samples in accordance with the compression control parameter to form a plurality of compressed samples for a compressed packet; and

transferring the compressed packet to the second memory device, the second memory device storing the compressed packet,

wherein one of the compression control parameters is a desired number of bits per compressed packet or a desired compression ratio and said compressing further comprises;

calculating a number of bits in the compressed samples per packet for one or more compressed packets;

comparing the number of bits in the compressed samples per packet to the desired number of bits per packet to determine a feedback parameter; and

adapting said compressing in accordance with the feedback parameter.

9. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for compressing waveform data for storage in the second memory device, comprising:

receiving a request at the memory controller from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format;

receiving one or more compression control parameters from the processor at compression logic integrated with the memory controller;

receiving the plurality of samples at the compression logic in the memory controller from the first memory device in response to the request from the processor;

the compression logic compressing the plurality of samples in accordance with the compression control parameter to form a plurality of compressed samples for a compressed packet; and

transferring the compressed packet to the second memory device, the second memory device storing the compressed packet,

wherein the compressed packet further includes a header portion and a payload portion, the method further comprising;

providing at least one of the compression control parameters in the header portion; and

providing the plurality of compressed samples in the payload portion.

10. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, a method for decompressing waveform data retrieved from the second memory device, comprising:

receiving at the memory controller a request from the processor to retrieve the waveform data from the second memory device, wherein the waveform data are represented by a plurality of compressed samples stored in the second memory device, wherein the plurality of compressed samples and one or more compression control parameters are contained in a compressed packet;

receiving the compressed packet from the second memory device at decompression logic integrated with the memory controller in response to the request;

the decompression logic decompressing the plurality of compressed samples of the compressed packet in accordance with the one or more compression control parameters to form a plurality of decompressed samples representing the waveform data; and

providing the plurality of decompressed samples to the first memory device, the first memory device storing the plurality of decompressed samples for access by the processor,

wherein a first one of compression control parameters is a data type parameter of the compressed samples, the data type parameter indicating an integer data format or a floating-point data format, wherein for the integer data format, the compressed packet includes compressed sign and mantissa data of the plurality of compressed samples, and for the floating-point data format, the compressed packet includes compressed floating-point exponent, sign and mantissa data of the plurality of compressed samples, the method further comprising;

configuring said decompressing to process the compressed sign and mantissa data to generate a first sign bit and a first plurality of mantissa bits of each decompressed sample when the data type parameter indicates the integer data format; and

configuring said decompressing to process the compressed floating-point exponent, sign and mantissa data of the plurality of compressed samples to generate a second sign bit, a second plurality of mantissa bits and a plurality of floating-point exponent bits of each decompressed sample when the data type parameter indicates the floating-point data format.

11. The method of claim 10, wherein the one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said decompressing applies lossless decompression operations or lossy decompression operations to the plurality of compressed samples in accordance with the compression mode parameter.

12. The method of claim 10, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the integer data format, said decompressing further comprising:

applying lossless decompression operations or lossy decompression operations in accordance with the compression mode parameter to the compressed sign and mantissa data to produce the first sign bit and the first plurality of mantissa bits of each decompressed sample in accordance with the integer data format.

13. The method of claim 10, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the floating-point data format, said decompressing further comprising:

extracting the compressed floating-point exponent data and the compressed sign and mantissa data from the compressed packet;

applying lossless decompression operations to the compressed floating-point exponent data to form a plurality of decompressed floating-point exponents;

applying lossless decompression operations or lossy decompression operations to the compressed sign and mantissa data in accordance with the compression mode parameter to form a plurality of decompressed signs and mantissas; and

combining the decompressed floating-point exponents with corresponding ones of the decompressed signs and mantissas to form the decompressed samples in accordance with the floating-point data format.

14. The method of claim 10, wherein the system includes a plurality of processors integrated on the chip, the memory controller receiving requests form one or more of the processors to read respective waveform data from the second memory device, wherein the respective waveform data are represented by respective pluralities of compressed samples stored in the second memory device, wherein said decompressing is applied to the respective pluralities of compressed samples to form respective pluralities of decompressed samples.

15. The method of claim 10, wherein the memory controller further comprises a direct memory access controller, wherein the decompression logic is integrated with the direct memory access controller to perform said decompressing.

16. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for compressing waveform data for storage in the second memory device, comprising:

the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format, the memory controller to retrieve the plurality of samples from the first memory device in response to the request; and

compression logic integrated with the memory controller, the compression logic coupled to receive the plurality of samples retrieved from the first memory device and one or more compression control parameters from the processor, wherein the compression logic is operable to compress the plurality of samples in accordance with the one or more compression control parameters to form a plurality of compressed samples for a compressed packet, the compression logic coupled to provide the compressed packet to the second memory device for said storage,

wherein one of the compression control parameters is a desired number of bits per compressed packet or a desired compression ratio, and said compression logic further comprises;

logic to calculate a number of bits in the compressed samples per packet for one or more compressed packets;

logic to compare the number of bits of compressed samples per packet to the desired number of bits per compressed packet to determine a feedback parameter; and

logic to adapt compression operations in accordance with the feedback parameter.

17. The apparatus of claim 16, wherein one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said compression logic is operable in the lossless compression mode or the lossy compression mode in accordance with the compression mode parameter.

18. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for compressing waveform data for storage in the second memory device, comprising:

the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format, the memory controller to retrieve the plurality of samples from the first memory device in response to the request; and

compression logic integrated with the memory controller, the compression logic coupled to receive the plurality of samples retrieved from the first memory device and one or more compression control parameters from the processor, wherein the compression logic is operable to compress the plurality of samples in accordance with the one or more compression control parameters to form a plurality of compressed samples for a compressed packet, the compression logic coupled to provide the compressed packet to the second memory device for said storage,

wherein a first one of the compression control parameters is a data type parameter of the samples, the data type parameter indicating the integer data format or the floating-point data format, wherein for the integer data format, each sample consists of a first sign bit and a first plurality of mantissa bits and for the floating-point data format, each sample consists of a second sign bit, a second plurality of mantissa bits and a plurality of floating-point exponent bits, the compression logic further comprising;

first logic to compress sign bits and mantissa bits of respective samples;

second logic to compress floating-point exponent bits of respective samples;

logic to provide the first sign bit and the first plurality of mantissa bits of each sample to the first logic when the data type parameter indicates the integer data format; and

logic to provide the second sign bit and the second plurality of mantissa bits of each sample to the first logic and to provide the plurality of floating-point exponent bits to the second logic when the data type parameter indicates the floating-point data format.

19. The apparatus of claim 18, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the integer data format, wherein said first logic is operable in the lossless compression mode or the lossy compression mode in accordance with the compression mode parameter.

20. The apparatus of claim 18, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the floating-point data format, wherein said first logic is operable in the lossless compression mode or the lossy compression mode in accordance with the compression mode parameter and said second logic is operable in the lossless compression mode.

21. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for compressing waveform data for storage in the second memory device, comprising:

the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to write the waveform data to the second memory device, wherein the waveform data comprise a plurality of samples represented in an integer data format or a floating-point data format, the memory controller to retrieve the plurality of samples from the first memory device in response to the request; and

compression logic integrated with the memory controller, the compression logic coupled to receive the plurality of samples retrieved from the first memory device and one or more compression control parameters from the processor, wherein the compression logic is operable to compress the plurality of samples in accordance with the one or more compression control parameters to form a plurality of compressed samples for a compressed packet, the compression logic coupled to provide the compressed packet to the second memory device for said storage,

wherein the compressed packet further includes a header portion and a payload portion, the compression logic further comprising;

logic to provide at least one of the compression control parameters to the header portion; and

logic to provide the plurality of compressed samples to the payload portion.

22. The apparatus of claim 21, wherein the system includes a plurality of processors integrated on the chip, wherein the memory controller is coupled to one or more of the processors to receive requests from respective processors to write respective waveform data to the second memory device, wherein said compression logic is applied to respective pluralities of samples to produce respective pluralities of compressed samples.

23. The apparatus of claim 21, wherein the memory controller further comprises a direct memory access controller, wherein the compression logic is integrated with the direct memory access controller.

24. In a system including a processor, a memory controller and a first memory device integrated on a chip and a second memory device located off the chip, an apparatus for decompressing waveform data retrieved from the second memory device, comprising:

the memory controller coupled to the processor and the first memory device, wherein the memory controller is operable to receive a request from the processor to read the waveform data from the second memory device, wherein the waveform data are represented by a plurality of compressed samples stored in the second memory device, wherein the plurality of compressed samples and one or more compression control parameters are contained in a compressed packet, the memory controller coupled to the second memory device to retrieve the compressed packet from the second memory device in response to the request; and

decompression logic integrated with the memory controller, the decompression logic coupled to receive the compressed packet retrieved from the second memory device, wherein the decompression logic is operable to decompress the plurality of compressed samples in accordance with the one or more compression control parameters to form a plurality of decompressed samples representing the waveform data, the decompression logic coupled to provide the plurality of decompressed samples to the first memory device, the first memory device storing the plurality of decompressed samples for access by the processor,

wherein a first one of compression control parameters is a data type parameter of the compressed samples, the data type parameter indicating an integer data format or a floating-point data format, wherein for the integer data format, the compressed packet includes compressed sign and mantissa data of the plurality of compressed samples, and for the floating-point data format, the compressed packet includes compressed floating-point exponent, sign and mantissa data of the plurality of compressed samples, the decompression logic further comprising;

first logic to decompress compressed sign and mantissa data of respective compressed samples to form decompressed signs and mantissas;

second logic to decompress compressed floating-point exponent data of respective compressed samples to form decompressed floating-point exponents;

logic to provide the compressed sign and mantissa data of the compressed packet to the first logic when the data type parameter indicates the integer data format; and

logic to provide the compressed sign and mantissa data of the compressed packet to the first logic and to provide the compressed floating-point exponent data of the compressed packet to the second logic when the data type parameter indicates the floating-point data format.

25. The apparatus of claim 24, wherein the one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said decompression logic is operable to apply lossless decompression operations or lossy decompression operations in accordance with the compression mode parameter.

26. The apparatus of claim 24, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the integer data format, wherein said first logic is operable to apply lossless decompression operations or lossy decompression operations in accordance with the compression mode parameter.

27. The apparatus of claim 24, wherein a second one of the compression control parameters is a compression mode parameter indicating a lossless compression mode or a lossy compression mode, wherein said data type parameter indicates the floating-point data format, wherein said first logic is operable in the lossless compression mode or the lossy compression mode in accordance with the compression mode parameter and said second logic is operable in the lossless compression mode, said compression logic further comprising:

logic to combine the decompressed floating-point exponents with corresponding ones of the decompressed signs and mantissas to form the decompressed samples in accordance with the floating-point data format.

28. The apparatus of claim 24, wherein the system includes a plurality of processors integrated on the chip, wherein the memory controller is coupled to one or more of the processors to receive requests from respective processors to read respective waveform data from the second memory device, wherein the respective waveform data are represented by respective pluralities of compressed samples stored in the second memory device, said decompression logic applied to the respective pluralities of compressed samples to form respective pluralities of decompressed samples.

29. The apparatus of claim 24, wherein the memory controller further comprises a direct memory access controller, wherein the decompression logic is integrated with the direct memory access controller.