Methods of manufacturing three-dimensional semiconductor devices
First Claim
1. A method of manufacturing a three-dimensional semiconductor device, comprising:
- forming a peripheral structure on a peripheral circuits region of a substrate,the peripheral structure including peripheral circuits;
recessing a cell array region of the substrate to form a concave region in the substrate,the concave region having a bottom surface lower than a top surface of the peripheral structure;
forming a stacked layer structure conformally covering the substrate in which the concave region is formed,the stacked layer structure including a plurality of layers sequentially stacked, andthe stacked layer structure having a lower top surface in the cell array region of the substrate compared to a top surface of the stacked layer structure in the peripheral circuits region of the substrate;
forming a planarization stop layer that conformally covers the stacked layer structure; and
planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.
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Abstract
According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.
40 Citations
20 Claims
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1. A method of manufacturing a three-dimensional semiconductor device, comprising:
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forming a peripheral structure on a peripheral circuits region of a substrate, the peripheral structure including peripheral circuits; recessing a cell array region of the substrate to form a concave region in the substrate, the concave region having a bottom surface lower than a top surface of the peripheral structure; forming a stacked layer structure conformally covering the substrate in which the concave region is formed, the stacked layer structure including a plurality of layers sequentially stacked, and the stacked layer structure having a lower top surface in the cell array region of the substrate compared to a top surface of the stacked layer structure in the peripheral circuits region of the substrate; forming a planarization stop layer that conformally covers the stacked layer structure; and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of manufacturing a three-dimensional semiconductor device, comprising:
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forming a concave region in a substrate including a cell array region and a peripheral circuits region, the concave region having a bottom surface parallel to a top surface of the substrate and a sidewall between the cell array region and the peripheral circuits region; forming a stacked layer structure conformally covering the bottom surface and the sidewall of the concave region, the stacked layer structure including a plurality of layers sequentially stacked, and the stacked layer structure having a lowest top surface over the cell array region and a highest top surface over the peripheral circuits region; forming a planarization stop layer conformally covering the stacked layer structure; and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure. - View Dependent Claims (12, 13, 14, 15)
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16. A method for manufacturing a three-dimensional semiconductor device comprising:
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forming a stacked layer structure that conformally covers at least a first and a second surface of a substrate and at least part of a peripheral structure on a peripheral circuits region of a substrate, the second surface of the substrate defining a sidewall between the first surface of the substrate and a top surface of the peripheral circuits region of the substrate, the stacked layer structure including a plurality of layers sequentially stacked, and the stacked layer structure having a top surface over the first surface of the substrate that is lower compared to a top surface of the stacked layer structure over the peripheral structure; forming a planarization stop layer that conformally covers the stacked layer structure; and planarizing the stacked layer structure using at least part of the planarization stop layer as a planarization end point to expose top surfaces of segments of the layers extending parallel to the second surface of the substrate. - View Dependent Claims (17, 18, 19, 20)
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Specification