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Field sequential color mode liquid crystal display

  • US 8,643,587 B2
  • Filed: 12/04/2006
  • Issued: 02/04/2014
  • Est. Priority Date: 02/09/2006
  • Status: Active Grant
First Claim
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1. A field sequential color (FSC) mode liquid crystal display (LCD), comprising:

  • a controller configured to operate in response to an external adjustment;

    a direct-current-to-direct-current (DC/DC) converter configured to convert a battery voltage into a driving voltage under control of the controller;

    a color light emitting diode (LED) backlight including first, second, and third color LED arrays connected in parallel and configured to be operated by the driving voltage outputted from the DC/DC converter;

    an FSC generator configured to generate first, second, and third color PWM signals as field sequential signals according to an internal sawtooth voltage and a dimming voltage; and

    a 3-channel current source configured to generate first, second, and third driving currents flowing through the first, second, and third color LED arrays of the color LED backlight, respectively, the 3-channel current source comprising respective on/off switching paths for the first, second, and third driving currents respectively controlled according to the first, second, and third color PWM signals generated from the FSC generator to adjust luminances of the first, second, and third color LED arrays of the color LED backlight, whereinthe FSC generator comprises;

    a sawtooth voltage generating unit configured to generate the internal sawtooth voltage;

    a comparing unit configured to compare the sawtooth voltage with the dimming voltage to output a PWM signal; and

    an FSC logic unit configured to divide the PWM signal by two and four and operate a logic operation on the divided signals to generate the first, second, and third color PWM signals, andthe FSC logic unit comprises;

    a first binary counter configured to divide an output signal of the comparing unit by two to generate a first divided signal;

    a second binary counter configured to divide an output signal of the first binary counter by two to generate a second divided signal;

    an inverter unit configured to invert the first divided signal and the second divided signal to output a first inverted signal and a second inverted signal;

    a first AND gate unit configured to perform a logical sum (AND) operation of the first and second inverted signals to output a first logic signal, an AND operation of the first divided signal and the second inverted signal to output a second logic signal, an AND operation of the first inverted signal and the second divided signal to output a third logic signal, and an AND operation of the first and second divided signals to output a fourth logic signal; and

    a second AND gate unit configured to perform a logical product (AND) operation of the first logic signal and the PWM signal to output a first color PWM signal, an AND operation of the second logic signal and the PWM signal to output a second color PWM signal, an AND operation of the third logic signal and the PWM signal to output a third color PWM signal, and an AND operation of the fourth logic signal and the PWM signal to output the second color PWM signal.

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