Method and system for modeling a bus for a system design incorporating one or more programmable processors

• US 8,644,305 B2
• Filed: 01/22/2008
• Issued: 02/04/2014
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Clark, Neville A., Torossian, James R.
• Primary Examiner(s): Kang, Suk Jin
• Application Number:
  US12/017,939
• Publication Number:
  US 20080235415A1
• Time in Patent Office: 2,205 Days
• Field of Search: None
• US Class Current: 370/362
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.

Claims

1. A method for processing data through a virtual bus structure model for simulating system designs including one or more programmable processors in a host processing system, the method comprising:

indicating that a transaction being simulated in the host processing system is available for transfer through the virtual bus structure model;

dividing transaction data of the transaction into one or more data payloads, wherein each data payload has one or more data beats;

setting a length of the data payload to be transferred through the virtual bus structure model that comprises specifying a number of the data beats in the payload committed to be transferred through the virtual bus structure model;

committing to a transfer of the specified number of the data beats in the at least one of the data payloads; and

routing the committed number of the data beats in the at least one of the data payloads through the virtual bus structure model.

2. The method of claim 1, further comprising:

storing the time at which a request for routing of the committed at least one data payload is made; and

storing the time at which the request for routing of the data payload is accepted.

3. The method of claim 2, wherein said storing the time at which a request for routing of the committed at least one data payload is made comprises setting a variable indicating the time.

4. The method of claim 2, further comprising;

indicating that a subsequent data payload is available for transfer; and

storing the time at which the subsequent data payload is available for transfer.

5. The method of claim 1, further comprising issuing a status identifier for each data beat in the committed at least one data payload.

6. The method of claim 1, further comprising issuing a status identifier for the entire committed at least one at least one data payload.

7. The method of claim 1, wherein said setting the length of the data payload comprises setting the data payload length such that start and end bytes of the payload are either start and end bytes of the transaction, respectively, or are located at a beat-aligned boundary between the start and end bytes of the transaction.

8. The method of claim 1, wherein said setting the length of the data payload comprises setting the data payload length such that the data payload length corresponds to a number of data beats of data that are guaranteed to be delivered on contiguous clock cycles.

9. A system for processing data in a transaction being simulated in a host processing system comprising:

a virtual bus structure model;

a data sender device model;

a data recipient device model;

an indication module configured to indicate that transaction data of the transaction being simulated in the host processing system is available for transfer through the virtual bus structure model from the data sender device model to the data recipient device model;

a data payload module configured to divide the transaction data of the transaction into one or more data payloads, wherein each data payload has one or more data beats, the data payload module configured to set a length of the data payload to be transferred through the virtual bus structure model that comprises specifying a number of the data beats in the payload committed to be transferred through the virtual bus structure model, and wherein the data payload module is configured to commit to a transfer the specified number of the data beats in the data payload; and

a routing module configured to route the committed number of the data beats in at least one of the data payloads from the data sender device model through the virtual bus structure model to the data recipient device model.

10. The system of claim 9, further comprising:

a storage medium configured to store a time at which a request for routing of the data payload is made by the data sender device model and a time at which the request for routing of the at least one data payload is accepted by the data recipient device model.

11. The system of claim 10, wherein the indication module is configured to indicate that a subsequent data payload is available for transfer.

12. The system of claim 10, wherein the storage medium is further configured to store a pointer to a buffer containing the subsequent data payload available for transfer in the transaction.

13. The system of claim 12, wherein the routing module is further configured to call a function requesting the stored pointer.

14. The system of claim 9, wherein the routing module is further configured to route an acknowledgement of the receipt of the at least one data payload by the data recipient device model back to the data sender device model.

15. The system of claim 9, wherein the data payload module is further configured to set the data payload length such that start and end bytes of the payload are either start and end bytes of the transaction data, respectively, or are located at a beat-aligned boundary between the start and end bytes of the transaction data.

16. The system of claim 9, wherein the data payload module is further configured to set the data payload length such that the data payload length corresponds to a number of data beats of data that are guaranteed to be delivered on contiguous clock cycles.

17. A computer program product comprising a non-transitory computer usable medium having control logic recorded thereon for enabling a processor in a host processing system to model data flow through a virtual bus structure model for simulating system designs including one or more programmable processors, said control logic comprising:

first computer readable program code means for enabling the processor to indicate that a transaction being simulated in the host processing system is available for transfer through the virtual bus structure model;

second computer readable program code means for enabling the processor to divide transaction data of the transaction into one or more data payloads, wherein each data payload has one or more data beats;

third computer readable program code means for enabling the processor to set a length of the data payload to be transferred through the virtual bus structure model that comprises specifying a number of the data beats in the payload committed to be transferred through the virtual bus structure model;

fourth computer readable program code means for enabling the processor to commit to a transfer of the specified number of the data beats in the data payload; and

fifth computer readable program code means for enabling the processor to route the committed number of the data beats in the at least one of the data payloads through the virtual bus structure model.

18. The computer program product of claim 17, further comprising:

sixth computer readable program code means for enabling the processor to store the time at which a request for routing of the at least one data payload is made;

seventh computer readable program code means for enabling the processor to queue the at least one data payload until a data recipient device model is ready to accept the at least one data payload; and

eighth computer readable program code means for enabling the processor to store the time at which the request for routing of the at least one data payload is accepted.

19. The computer program product of claim 18, further comprising ninth computer readable program code means for enabling the processor to indicate that a subsequent data payload is available for transfer.

20. The computer program product of claim 18, wherein the seventh computer readable program code means includes ninth computer readable program code means for enabling the processor to store a pointer to a buffer containing the data available for transfer in the transaction.

21. The computer program product of claim 20, wherein the fifth computer readable program code means includes computer readable program code means for enabling the processor to call a function requesting the stored pointer.

22. The computer program product of claim 17, wherein the second computer readable program code means includes computer readable program code means for enabling the processor to set the data payload length such that start and end bytes of the payload are either start and end bytes of the transaction data, respectively, or are located at a beat-aligned boundary between the start and end bytes of the transaction.

23. The computer program product of claim 17, wherein the second computer readable program code means includes computer readable program code means for enabling the processor to set the data payload length such that the data payload length corresponds to a number of data beats of data that are guaranteed to be delivered on contiguous clock cycles.