Memory device for concurrent and pipelined memory operations

• US 8,645,617 B2
• Filed: 10/15/2009
• Issued: 02/04/2014
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian, Haukness, Brent Steven
• Primary Examiner(s): Bradley, Matthew
• Application Number:
  US13/126,726
• Publication Number:
  US 20110208905A1
• Time in Patent Office: 1,573 Days
• Field of Search: 711/168, 711/169, 711/103, 711/154
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.

Claims

1. A memory device, comprising:

a memory storage space having a plurality of storage units, each storage unit representing a minimum amount of storage space that must be programmed together;

a write data register to hold data for use in programming of at least one of the storage units, in connection with a multiple cycle state change operation;

a sense amplifier unit to read data from any of the storage units;

an input/output (IO) interface; and

internal routing to

(i) couple the sense amplifier unit with the write data register, to feed back storage unit contents for use in the multiple cycle state change operation, and

(ii) couple read data from one of the storage units to the IO interface, contemporaneous with the multiple cycle state change operation.

2. The memory device of claim 1, where:

the device further comprises at least one data buffer operatively positioned (i) in between the sense amplifier unit and the IO interface and (ii) also in between the write data register and the IO interface; and

the internal routing is adapted to route program data from the at least one buffer to the write data register and to route read data from the sense amplifier unit to the at least one buffer.

3. The memory device of claim 1, where:

the memory device further comprises at least two buffers, operatively positioned in between the sense amplifier unit and the IO interface, each buffer sized to at least hold a memory page; and

the internal routing includes a switching mechanism adapted to, while a multiple cycle state change operation is in progress, alternatively route data from the sense amplifier unit to (i) the write data register, for use in connection with the multiple cycle state change operation, and (ii) a dynamically assigned one of the buffers, to transfer the read data from the sense amplifier unit to the dynamically assigned one of the buffers contemporaneous with the multiple cycle state change operation.

4. The memory device of claim 3, where the multiple cycle state change operation includes a write operation, and the switching mechanism is to transfer the read data from the dynamically assigned one of the buffers to the output interface while a write operation is in progress.

5. The memory device of claim 3, where the internal routing is adapted to load a page corresponding to the program data into a second dynamically assigned buffer in association with a write operation, such that a storage unit of the memory storage space that is the subject of a write operation may be read contemporaneous with the write operation, notwithstanding any transitory state of the storage unit of the memory storage space that is the subject of the write operation, by reading data associated with the write operation from the second dynamically assigned buffer.

6. The memory device of claim 3, where the internal routing includes a crossbar having a width at least equal to the page size, the crossbar adapted to route data between (i) either of the write data register or the sense array, and (ii) any one of the at least two buffers.

7. The memory device of claim 6, where each one of the at least two buffers is externally addressable through the IO interface, such that an external device can selectively cause loading of data in any specific one of the at least two buffers.

8. The memory device of claim 3, where:

plural cycles of the multiple cycle state change operation each include a verify operation that compares contents of a storage unit of the memory storage space with contents of the write data register; and

the internal routing is configured to inhibit transfer of the read data to a dynamically assigned one of the buffers during a verify operation.

9. The memory device of claim 3, where:

one of the buffers is adapted to store a copy of data originally stored in the write data register for reference during the state change operation, to permit reading of that data originally stored in the write data register contemporaneous with the multiple cycle state change operation; and

the memory device is adapted to permit reading of data associated with any one of the plurality of storage units of the memory storage space contemporaneous with a state change operation, by reading requested data from one of the storage units that is not the subject of contemporaneous state change from the memory storage space, and by reading the data originally stored in the write data register from the one of the buffers.

10. The memory device of claim 3, where dynamic assignment is performed by assignment logic, resident on-board the memory device.

11. The memory device of claim 3, where the switching mechanism is adapted to transfer the read data from the sense amplifier unit to the dynamically assigned buffer while an erase operation is in progress.

12. The memory device of claim 1, where:

the memory device further comprises at least three buffers, each sized to at least hold a memory page;

the internal routing is configured to both (i) store a copy of the read data in dynamically assigned first one of buffers, and (ii) transfer the read data from the first one of the buffers to the IO interface while the multiple cycle state change operation is in progress;

the internal routing is further adapted to load program data into a dynamically assigned second one of the buffers, and to permit reading of the program data from the second one of the buffers, contemporaneous with the multiple cycle state change operation; and

the memory device is adapted to permit reading of data associated with any one of the plurality of storage units contemporaneous with the multiple cycle state change operation, by reading each unit not the subject of contemporaneous state change from the memory storage space, and by reading the program data from the one of the buffers.

13. The memory device of claim 12, where the state change operation includes a multiple cycle, program-verify operation.

14. The memory device of claim 12, where the internal routing is to (a) transfer data between sense amplifier unit and any one of the at least three buffers, and (b) transfer data between the sense amplifier unit and the write data register.

15. The memory device of claim 14, where the memory device further comprises control logic adapted to interleave a memory read operation in between cycles of the multiple cycle state change operation, the control logic adapted to queue the memory read operation during at least a verify phase of one of the cycles of the multiple cycle state change operation, and to perform the read operation in between cycles of the multiple cycle state change operation.

16. The memory device of claim 1, embodied as a flash memory device.

17. The memory device of claim 1, where the internal routing is adapted to, within a single program-verify cycle, (i) couple the sense amplifier unit with the write data register, to feed back storage unit contents for use in the multiple cycle state change operation, and also (ii) couple read data from one of the storage units to the IO interface.

18. A memory device, comprising:

a plurality of storage units of storage area;

a sense mechanism to read data values from any of the storage units;

a write data register to be used in programming data values into any of the storage units;

a plurality of buffers;

a crossbar coupling (i) each of the plurality of buffers with (ii) a selective one of either the write data register or the sense mechanism; and

an input/output (IO) interface adapted to operatively couple each of the plurality of buffers with an external bus.

19. The memory device of claim 18, embodied as a flash memory device.

20. The memory device of claim 18, where each storage unit represents at least one of (i) the minimum amount of memory space that can be separately programmed or (ii) the minimum amount of memory space that can be separately erased.

21. The memory device of claim 18, where:

the device is adapted to program individual ones of the storage units by a multiple cycle, program-verify operation; and

the device further comprises means for permitting the read of specific data contemporaneous with an uncompleted multiple cycle, program-verify operation of the specific data.

22. The memory device of claim 18, where:

the device is adapted to program individual ones of the storage units by a multiple cycle, program-verify operation; and

the device further comprises control logic adapted to interleave a read operation between cycles associated with the program-verify operation.

23. The memory device of claim 18, where:

the device is adapted to program individual ones of the storage units by a multiple cycle, erase operation; and

the device further comprises control logic adapted to interleave a read operation between cycles associated with the erase operation.

24. The memory device of claim 18, where the device is adapted to permit read of data for one of the plurality of storage units of the storage area from a first one of the plurality of buffers via the IO interface, and to simultaneously transfer data associated with a subsequent read operation of one of the storage units via the crossbar to a second one of the plurality of buffers.

25. The memory device of claim 18, where the device further comprises control logic adapted to (i) permit programming of first data into one of the plurality of storage units of the storage area using the write data register, (ii) queue second data associated with a subsequent programming operation of one of the plurality of storage units in one of the plurality of buffers, and (iii), following completion of the programming of the first data, transfer the second data via the crossbar from the one of the plurality of buffers to the write data register.

26. The memory device according to claim 25, where the device is further adapted to permit read of the first data from a second one of the plurality of buffers, and adapted to permit read of the second data from the first one of the plurality of buffers, each notwithstanding contemporaneous performance by the memory device of programming of one of the plurality of storage units of the storage area.

27. A memory device, comprising:

a memory array;

means for tracking usage of each one of multiple buffers within the device;

means for, in connection with a first memory operation directed to the memory array, identifying a first one of the buffers as not currently being used, and for responsively loading first data associated with at least a page of the memory array into the first one of the buffers;

means for, in connection with a second memory operation directed to the memory array, identifying a second one of the buffers as not currently being used, and for responsively loading second data associated with at least a page of the memory array into the second one of the buffers;

means for concurrently performing the first memory operation and the loading of the second data; and

means for, responsive to the tracking, performing the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions.

28. A method of operating a memory array, comprising:

tracking usage of each one of multiple buffers within the memory array;

in connection with a first memory operation directed to the memory array, identifying a first one of the buffers as not currently being used and responsively loading first data associated with at least a page of the memory array into the first one of the buffers;

in connection with a second memory operation directed to the memory array, identifying a second one of the buffers as not currently being used and responsively loading second data associated with at least a page of the memory array into the second one of the buffers;

concurrently performing the first memory operation and the loading of the second data; and

responsive to the tracking, performing the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions.

29. The method of claim 28, where tracking includes tracking each one of the multiple buffers in a flash memory controller.

30. The method of claim 28, where the first memory operation includes a multiple cycle program-verify operation.

31. The method of claim 30, where each cycle of the multiple cycle program-verify operation includes a program phase and a verify phase, and where concurrently performing includes loading the second data during the program phase and inhibiting loading of the second data during the verify phase.

32. The method of claim 28, where each of the first memory operation includes a read operation.

33. The method of claim 28, wherein each of the first memory operation and the second memory operation include a programming operation, the method further comprising loading a write data register with a copy of the first data from the first one of the buffers, programming the first data, and following completion of programming the first data, loading the write data register with a copy of the second data from the second one of the buffers.

34. An apparatus comprising instructions stored on non-transitory machine readable storage media, the apparatus being adapted for use in the control of at least one memory device having multiple buffers that are each used to hold data during memory operations directed to a memory array, the at least one memory device adapted to concurrently perform each of a first memory operation directed to the memory array and a second memory operation directed to the memory array using different ones of the multiple buffers, the instructions when executed adapted to cause a machine to:

track usage of each one of multiple buffers resident within the memory device;

identify, in connection with the first memory operation, a first one of the buffers as not currently being used, and to responsively load first data associated with at least a page of memory in the device into the first one of the buffers;

identify, in connection with the second memory operation, a second one of the buffers as not currently being used, and to responsively load second data associated with at least a page of memory in the device into the second one of the buffers; and

responsive to the tracking, perform the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions.

35. The apparatus of claim 34, adapted for use by a memory controller, the instructions comprising firmware and the machine readable storage media comprising a read-only memory device.

36. An apparatus for use with a memory array serviced by a plurality of buffers, each buffer coupled to an interface with a system data bus, the apparatus comprising:

a state machine to track utilization of each one of the plurality of buffers; and

a controller-resident command generator, the command generator coupled to the state machine, the command generator to generate buffer-specific commands in response to state machine contents.

37. The apparatus of claim 36, wherein the state machine is resident with the memory array and the plurality of buffers in a memory device.

38. The apparatus of claim 36, wherein the state machine is controller-resident.

39. The apparatus of claim 36, wherein the buffer-specific commands include at least one of:

a command to transfer data from a sense amplifier unit to a specific buffer;

a command to transfer data from a specific buffer to the system data bus;

a command to write program data into a specific buffer;

a command to read data that is the subject of a program command from a specific buffer;

a command to copy data from a specific buffer into a write data register;

or

a command to non-destructively copy data from a specific buffer into the write data register.

40. The apparatus of claim 36, wherein the buffer specific commands include a buffer address field.

41. A memory device, comprising:

a memory array having a plurality of storage units, each storage unit representing a minimum amount of storage space that must be programmed together;

a write data register to hold data for use in programming of at least one of the storage units, in connection with a multiple cycle state change operation, where the data in the write data register is changed during the multiple cycle state change operation;

a buffer to hold a copy of the data loaded into the write data register, and in which the data is not changed during the multiple cycle state change operation; and

control logic to serve a read request for the data undergoing programming in the at least one of the storage units from the buffer during the multiple cycle state change operation.

42. The memory device of claim 41, further comprising a state machine that identifies a storage location, including the buffer or the memory storage space, holding a true copy of said data.

43. The memory device of claim 42, further comprising plural buffers, where the control logic assigns each one of the plural buffers on an ad hoc basis for both use in loading a copy of write data into the write data register and in serving a copy of said data in connection with a read request directed to said data during the multiple cycle state change operation.