Random number generator including a variable frequency oscillator
First Claim
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1. A random number generator comprising:
- a variable frequency oscillator that comprises;
a selection circuit having multiple input terminals and an output terminal;
a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit comprising one or more buffer circuits to be selected by the selection circuit; and
an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and
a latch circuit connected to the variable frequency oscillator, whereinthe variable frequency oscillator outputs a signal having a variable frequency, where TH is a time in which a level of the output signal is high and TL is a time in which the level of the output signal is low,the latch circuit has a setup time TSET and a hold time THOLD, and
min(TH,TL)>
(TSET+THOLD).
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Abstract
A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.
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20 Claims
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1. A random number generator comprising:
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a variable frequency oscillator that comprises; a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit comprising one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator, wherein the variable frequency oscillator outputs a signal having a variable frequency, where TH is a time in which a level of the output signal is high and TL is a time in which the level of the output signal is low, the latch circuit has a setup time TSET and a hold time THOLD, and
min(TH,TL)>
(TSET+THOLD). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification