Electronic component package fabrication method and structure

• US 8,653,674 B1
• Filed: 09/15/2011
• Issued: 02/18/2014
• Est. Priority Date: 09/15/2011
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Darveaux, Robert Francis, Dunlap, Brett Arnold, Huemoeller, Ronald Patrick
• Primary Examiner(s): Diallo, Mamadou
• Application Number:
  US13/233,606
• Time in Patent Office: 887 Days
• Field of Search: 257678-733, 257787-796, 257E23001-E23194
• US Class Current: 257/786
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.

Claims

1. A method comprising:

coupling a redistribution pattern to an active surface of an electronic component to form a distributed electronic component, the entire redistribution pattern being coupled to the active surface;

coupling the redistributed electronic component to a carrier; and

overmolding the redistributed electronic component.

2. The method of claim 1 further comprising:

removing the carrier.

3. The method of claim 2 further comprising:

coupling a buildup dielectric layer to the redistribution pattern, the buildup dielectric layer comprising redistribution pattern terminal apertures exposing redistribution pattern terminals of the redistribution pattern.

4. The method of claim 3 further comprising:

coupling a buildup circuit pattern to the buildup dielectric layer, the buildup circuit pattern being coupled to the redistribution pattern terminals through the redistribution pattern terminal apertures.

5. The method of claim 4 further comprising:

coupling an outer dielectric layer to the buildup circuit pattern.

6. The method of claim 5 further comprising:

coupling interconnection balls to the buildup circuit pattern through land apertures of the outer dielectric layer.

7. The method of claim 1 wherein the active surface comprises bond pads, wherein the coupling a redistribution pattern to an active surface of an electronic component comprises:

coupling the redistribution pattern to the bond pads.

8. The method of claim 7 wherein the coupling a redistribution pattern to an active surface of an electronic component further comprises:

coupling a redistribution pattern dielectric layer to the active surface, the redistribution pattern dielectric layer comprising via apertures exposing the bond pads; and

coupling the redistribution pattern to the redistribution pattern dielectric layer, the redistribution pattern being coupled to the bond pads through the via apertures.

9. The method of claim 4 wherein the buildup circuit pattern comprises traces comprising lands.

10. The method of claim 9 wherein the buildup circuit pattern further comprises an electrically conductive plane.

11. A method comprising:

providing a wafer comprising a plurality of electronic component integrally connected together, the electronic components comprising active surfaces comprising bond pads;

forming redistribution patterns on the active surfaces to form redistributed electronic components integrally connected in the wafer, the redistribution patterns redistributing the pattern of the bond pads to a pattern of redistribution pattern terminals of the redistribution patterns;

singulating the redistributed electronic components;

mounting the redistributed electronic components to a carrier; and

overmolding the redistributed electronic components in a package body.

12. The method of claim 11 further comprising:

removing the carrier, wherein the package body supports an array comprising the redistributed electronic components and the package body.

13. The method of claim 12 further comprising:

coupling a buildup dielectric layer to a first surface of the package body and the redistribution patterns; and

forming redistribution pattern terminal apertures through the buildup dielectric layer to expose the redistribution pattern terminals.

14. The method of claim 13 further comprising:

forming buildup circuit patterns coupled to the redistribution pattern terminals through the redistribution pattern terminal apertures, the buildup circuit patterns redistributing the pattern of the redistribution pattern terminals to a pattern of lands of the buildup circuit patterns.

15. The method of claim 14 further comprising singulating the array to form a plurality of electronic component packages.

16. A method comprising:

providing an electronic component comprising an active surface comprising bond pads thereon;

coupling a redistribution pattern to the active surface and the bond pads, the entire redistribution pattern being coupled to the active surface;

coupling a buildup dielectric layer to the redistribution pattern; and

coupling a buildup circuit pattern to the buildup dielectric layer, the buildup circuit pattern being coupled to redistribution pattern terminals of the redistribution pattern through redistribution pattern terminal apertures of the buildup dielectric layer.

17. The method of claim 16 further comprising:

enclosing an inactive surface and sides of the electronic component in a package body.

18. The method of claim 17 wherein the package body comprises a first surface parallel to and coplanar with the redistribution pattern.

19. The method of claim 18 wherein the buildup dielectric layer is coupled to the first surface of the package body, the buildup circuit pattern comprising traces extending laterally outwards beyond the sides of the electronic component in a fan out-configuration.

20. The method of claim 19 wherein the buildup circuit pattern further comprises an electrically conductive plane.