Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a plurality of memory cells;
a pair of first and second local bit lines to which the plurality of memory cells are connected;
a pair of first and second write global bit lines;
a pair of first and second read global bit lines;
a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line;
a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line;
a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied;
a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied;
a precharge circuit connected to the first and second local bit lines;
a write driver configured to control the first and second write global bit lines; and
a read circuit connected to the first and second local bit lines and the first and second read global bit lines.
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Accused Products
Abstract
A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.
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Citations
13 Claims
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1. A semiconductor memory device, comprising:
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a plurality of memory cells; a pair of first and second local bit lines to which the plurality of memory cells are connected; a pair of first and second write global bit lines; a pair of first and second read global bit lines; a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line; a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line; a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied; a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied; a precharge circuit connected to the first and second local bit lines; a write driver configured to control the first and second write global bit lines; and a read circuit connected to the first and second local bit lines and the first and second read global bit lines. - View Dependent Claims (2, 3, 4, 5, 11)
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6. A semiconductor memory device, comprising:
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a plurality of memory cells; a pair of first and second local bit lines to which the plurality of memory cells are connected; a pair of first and second write global bit lines; a pair of first and second read global bit lines; a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line; a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line; a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied; a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied; a write driver configured to control the first and second write global bit lines and having a function of turning on or off the first and second write transistors simultaneously; and a read circuit connected to the first and second local bit lines and the first and second read global bit lines. - View Dependent Claims (7, 8, 12)
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9. A semiconductor memory device, comprising:
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a plurality of memory cells; a pair of first and second local bit lines to which the plurality of memory cells are connected; a pair of first and second write global bit lines; a pair of first and second read global bit lines; a first write transistor having a source connected to a ground node to which a ground voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line; a second write transistor having a source connected to the ground node, a drain connected to the second local bit line, and a gate connected to the first write global bit line; a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied; a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied; a precharge circuit connected to the first and second local bit lines; a write driver configured to control the first and second write global bit lines; and a read circuit connected to the first and second local bit lines and the first and second read global bit lines. - View Dependent Claims (10, 13)
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Specification