High data rate interface with improved link synchronization

• US 8,670,457 B2
• Filed: 12/08/2004
• Issued: 03/11/2014
• Est. Priority Date: 12/08/2003
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, Jon James, Steele, Brian, Wiley, George Alan, Shekhar, Shashank
• Primary Examiner(s): Pham, Brenda H
• Application Number:
  US11/008,024
• Publication Number:
  US 20050204057A1
• Time in Patent Office: 3,380 Days
• Field of Search: 370/389, 370/454, 370/395.62, 370/503, 709/230, 709/200, 709/217, 709/218, 709/219, 709/231, 709/232, 709/238
• US Class Current: 370/454
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 65/1069 Session establishment or de-establishment
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 65/61 for supporting one-way streaming services, e.g. Internet radio
• CPC Class Codes: H04L 65/80 Responding to QoS
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04M 1/72409 by interfacing with external accessories hands-free H04M1/60
• CPC Class Codes: H04M 1/724097 Worn on the head
• CPC Class Codes: H04W 56/00 Synchronisation arrangements
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Claims

1. A method executed in a processor comprising a controller circuit for ensuring that all data signals are simultaneously being driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the method comprising the steps of:

disabling a host'"'"'s data line drivers prior to a last bit of a turn around 1 period of the reverse link encapsulation packet;

enabling the client'"'"'s line drivers at a beginning of the turn around 1 period of the reverse link encapsulation packet; and

simultaneously driving the data signals by the host and the client.

2. The method of claim 1 further comprising the step of toggling a strobe at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

3. The method of claim 1 wherein the turn around 1 period comprises a time period for the host'"'"'s line drivers to disable and the client'"'"'s line drivers to enable substantially simultaneously.

4. The method of claim 1 wherein the turn around 1 period comprises a time period greater than a sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.

5. A system comprising computer-readable storage medium encoded with a data structure for ensuring that all data signals are simultaneously being driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the system comprising:

a processor comprising a controller circuit;

means for disabling a host'"'"'s data line drivers prior to a last bit of a turn around 1 period of the reverse link encapsulation packet in the processor

means for enabling the client'"'"'s line drivers at a beginning of the turn;

around 1 period of the reverse link encapsulation packet in the processor; and

means for simultaneously driving the data signals in the processor by the host and the client.

6. The system of claim 5 further comprising a means for toggling a strobe at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

7. The system of claim 5 wherein the turn around 1 period comprises a time period for the host'"'"'s line drivers to disable and the client'"'"'s line drivers to enable substantially simultaneously.

8. The system of claim 5 wherein the turn around 1 period comprises a time period greater than a sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.

9. The system of claim 5 wherein the turn around 1 period comprises a time period greater than the sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.

10. A non-transitory computer readable storage media comprising program instructions which are hardware computer-executable to implement all data signals to be simultaneously driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the non-transitory computer-readable storage media comprising:

program instructions that cause a host'"'"'s data line drivers to be disabled prior to a last bit of a turnaround 1 period of the reverse link encapsulation packet;

program instructions that cause the client'"'"'s line drivers to be enabled at a beginning of the turnaround 1 period of the reverse link encapsulation packet; and

program instructions that cause the data signals to be driven by the host and the client simultaneously.

11. The non-transitory computer readable storage media of claim 10 further comprising program instructions that cause a strobe to be toggled at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

12. The non-transitory computer readable storage media of claim 10 wherein the turn around 1 period comprises a time period for the host'"'"'s line drivers to disable and the client'"'"'s line drivers to enable substantially simultaneously.

13. The non-transitory computer readable storage media of claim 10 wherein the turn around 1 period comprises a time period greater than a sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.

14. A method executed in a processor comprising a controller circuit for ensuring that all data signals are being driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the method comprising the steps of:

disabling a client'"'"'s data line drivers prior to a last bit of a turn around 2 period of the reverse link encapsulation packet;

enabling a host'"'"'s line drivers prior to an end of a turn around 2 period of the reverse link encapsulation packet; and

simultaneously driving the data signals by the host the client.

15. The method of claim 14 wherein a strobe is toggled at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

16. The method of claim 14 wherein the host'"'"'s line driver is enabled after a time period equal to a measured round trip delay following a beginning of the turn around 2 period.

17. A system for ensuring that all data signals are being driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the system comprising:

a processor comprising a controller circuit;

disabling a client'"'"'s data line drivers prior to a last bit of a turn around 2 period of the reverse link encapsulation packet in the processor;

enabling a host'"'"'s line drivers prior to an end of a turn around 2 period of the reverse link encapsulation packet in the processor; and

simultaneously driving the data signals by the host and the client.

18. The system of claim 17 wherein a strobe is toggled at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

19. The system of claim 17 wherein the host'"'"'s line driver is enabled after a time period equal to a measured round trip delay following a beginning of the turn around 2 period.

20. A non-transitory computer readable storage media comprising program instructions which are hardware computer-executable to implement all data signals to be driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the non-transitory computer-readable storage media comprising:

program instructions that cause a client'"'"'s data line drivers be disabled prior to a last bit of a turn around 2 period of the reverse link encapsulation packet;

program instructions that cause a host'"'"'s line drivers be enabled prior to an end of a turn around 2 period of the reverse link encapsulation packet; and

program instructions that cause the data signal to be driven simultaneously by the host and the client.

21. The non-transitory computer-readable storage media of claim 20 wherein a strobe is toggled at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

22. The non-transitory computer-readable storage media of claim 20 wherein the host'"'"'s line driver is enabled after a time period equal to a measured round trip delay following a beginning of the turn around 2 period.

23. A system comprising computer-readable storage medium encoded with a data structure for ensuring that all data signals are simultaneously being driven during a transmission of a reverse link encapsulation packet in a mobile display digital interface (MDDI) communication system, the system comprising:

a processor comprising a controller circuit configured to;

disable a host'"'"'s data line drivers prior to a last bit of a turn around 1 period of the reverse link encapsulation packet in the processor;

enable the client'"'"'s line drivers at a beginning of the turn around 1 period of the reverse link encapsulation packet in the processor; and

simultaneously drive the data signals in the processor by the host and the client.

24. The system of claim 23 wherein the controller circuit is further adapted to toggle a strobe at each bit boundary from a beginning of an all zero 1 field to an end of an all zero 2 field of the reverse link encapsulation packet.

25. The system of claim 23 wherein the turn around 1 period comprises a time period for the host'"'"'s line drivers to disable and the client'"'"'s line drivers to enable substantially simultaneously.

26. The system of claim 23 wherein the turn around 1 period comprises a time period greater than a sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.

27. The system of claim 23 wherein the turn around 1 period comprises a time period greater than the sum of a calculated round trip delay, a host driver disable time, and a client driver enable time.