Computer bus with enhanced functionality

• US 8,671,236 B2
• Filed: 06/06/2011
• Issued: 03/11/2014
• Est. Priority Date: 06/06/2011
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Inventors: Goldenberg, Dror, Fael, Doron, Adar, Gil
• Primary Examiner(s): Spittle, Matthew D
• Application Number:
  US13/153,477
• Publication Number:
  US 20120311220A1
• Time in Patent Office: 1,009 Days
• Field of Search: 710/305, 710/313, 710/314, 710/72, 710/74, 713/300, 713/323
• US Class Current: 710/305
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.

Claims

1. A method for computing, comprising:

connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins;

using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the peripheral device that the host device has an extended operational capability; and

sensing, at the peripheral device, that the at least one pin is floating, and operating in accordance with the extended operational capability of the host device,

wherein using the at least one pin comprises floating two of the pins on the bus that are specified as the ground pins, and wherein sensing that the at least one pin is floating comprises detecting that both of the two of the pins are floating as a condition for operating in accordance with the extended operational capability.

2. A method for computing, comprising:

connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; and

using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the peripheral device that the host device has an extended operational capability,

wherein the at least one pin is used to indicate an extended power budget provided by the host device.

3. The method according to claim 2, wherein using the at least one pin comprises floating the at least one pin.

4. The method according to claim 3, and comprising sensing, at the peripheral device, that the at least one pin is floating, and operating in accordance with the extended operational capability of the host device.

5. The method according to claim 2, wherein the extended power budget provides electrical power to the peripheral device while the host device is in a standby mode that is in excess of a basic power budget of the standby mode that is specified by the standard.

6. The method according to claim 2, wherein the at least one pin is used to indicate an extended communication capability provided by the host device.

7. The method according to claim 6, wherein the extended communication capability comprises support, via the bus, for a type of communication interface that is not provided by the standard.

8. The method according to claim 2, wherein the peripheral device comprises a network interface controller (NIC).

9. The method according to claim 2, wherein the bus is a PCI Express bus.

10. A method for computing, comprising:

connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; and

using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the peripheral device that the host device has an extended operational capability,

wherein the at least one pin is used to indicate an extended communication capability provided by the host device, wherein the extended communication capability comprises support, via the bus, for a type of communication interface that is not provided by the standard, and

wherein the communication interface is a Network Communications Services Interface (NCSI).

11. The method according to claim 10, wherein using the at least one pin comprises floating the at least one pin.

12. The method according to claim 10, wherein the bus is a PCI Express bus.

13. The method according to claim 10, wherein the peripheral device comprises a network interface controller (NIC).

14. A method for computing, comprising:

connecting a host device to a network interface controller (NIC) via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; and

using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the NIC that the host device has an extended operational capability,

wherein the extended operational capability comprises an extended budget of electrical power provided to the NIC while the host device is in a standby mode, and wherein the method comprises providing a wake-on-LAN (WOL) service from the NIC to the host device using the electrical power in the extended budget.

15. The method according to claim 14, wherein using the at least one pin comprises floating the at least one pin.

16. The method according to claim 14, wherein the bus is a PCI Express bus.

17. A method for computing, comprising:

connecting a peripheral device to a host device to via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins;

detecting in the peripheral device an extended operational capability of the host device by sensing an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pins,

wherein the electrical level of the at least one pin indicates that the host device provides an extended power budget while the host device is in a standby mode; and

operating the peripheral device in accordance with the extended operational capability.

18. The method according to claim 17, wherein sensing the electrical level comprises detecting that the at least one pin is floating.

19. The method according to claim 17, wherein the peripheral device comprises a network interface controller (NIC), and wherein operating the peripheral device comprises providing a wake-on-LAN (WOL) service from the NIC to the host device using electrical power provided by the extended power budget.

20. The method according to claim 17, wherein the electrical level of the at least one pin indicates that the host device has an extended communication capability.

21. A method for computing, comprising:

connecting a peripheral device to a host device to via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins;

detecting in the peripheral device an extended operational capability of the host device by sensing an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pins; and

operating the peripheral device in accordance with the extended operational capability,

wherein the electrical level of the at least one pin indicates that the host device has an extended communication capability, and

wherein the extended communication capability comprises support, via the bus, for a Network Communications Services Interface (NCSI) that is not provided by the standard, and wherein operating the peripheral device comprises communicating between the peripheral device and a service processor in the host device via the NCSI.

22. A computing device, comprising:

a host processor; and

a bus, which is coupled to the host processor and which is physically configured in accordance with a predefined standard, which specifies multiple connection pins of the bus, including a plurality of ground pins, the bus comprising at least one pin, selected from among the pins on the bus that are specified as the ground pins, that is used to indicate to a peripheral device connected to the bus that the computing device has an extended operational capability,

wherein the at least one pin is used to indicate an extended power budget provided by the host device.

23. The device according to claim 22, wherein the at least one pin floats to indicate the extended operational capability.

24. The device according to claim 23, and comprising the peripheral device, wherein the peripheral device comprises a sensing circuit, which is coupled to detect that the at least one pin is floating, so as to cause the peripheral device to operate in accordance with the extended operational capability of the host device.

25. The device according to claim 22, wherein the extended power budget provides electrical power to the peripheral device while the host device is in a standby mode that is in excess of a basic power budget of the standby mode that is specified by the standard.

26. The device according to claim 22, wherein the at least one pin is used to indicate an extended communication capability provided by the host device.

27. The device according to claim 26, wherein the extended communication capability comprises support, via the bus, for a type of communication interface that is not provided by the standard.

28. The device according to claim 22, wherein the peripheral device comprises a network interface controller (NIC).

29. A computing device, comprising:

a host processor; and

a bus, which is coupled to the host processor and which is physically configured in accordance with a predefined standard, which specifies multiple connection pins of the bus, including a plurality of ground pins, the bus comprising at least one pin, selected from among the pins on the bus that are specified as the ground pins, that is used to indicate that the computing device has an extended operational capability,

wherein the at least one pin floats to indicate the extended operational capability; and

a peripheral device connected to the bus, wherein the peripheral device comprises a sensing circuit, which is coupled to detect that the at least one pin is floating, so as to cause the peripheral device to operate in accordance with the extended operational capability of the host device,

wherein the at least one pin comprises two of the pins on the bus that are specified as the ground pins, and wherein the sensing circuit is configured to detect that both of the two of the pins are floating as a condition for operating in accordance with the extended operational capability.

30. A computing device, comprising:

a host processor; and

a bus, which is coupled to the host processor and which is physically configured in accordance with a predefined standard, which specifies multiple connection pins of the bus, including a plurality of ground pins, the bus comprising at least one pin, selected from among the pins on the bus that are specified as the ground pins, that is used to indicate to a peripheral device connected to the bus that the computing device has an extended communication capability,

wherein the extended communication capability comprises support, via the bus, for a type of communication interface that is not provided by the standard, and

wherein the communication interface is a Network Communications Services Interface (NCSI).

31. A computing device, comprising:

a host processor; and

a bus, which is coupled to the host processor and which is physically configured in accordance with a predefined standard, which specifies multiple connection pins of the bus, including a plurality of ground pins, the bus comprising at least one pin, selected from among the pins on the bus that are specified as the ground pins, that is used to indicate to a network interface controller (NIC) connected to the bus that the computing device has an extended operational capability,

wherein the extended operational capability comprises an extended budget of electrical power provided to the NIC while the host device is in a standby mode, and wherein the NIC is configured to provide a wake-on-LAN (WOL) service to the device using the electrical power in the extended budget.

32. A computing device, comprising:

a bus interface, which is configured to connect the computing device to a host device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins, and which comprises a sensing circuit, which is coupled to detect an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pin and to output a signal in response to the electrical level,

wherein the electrical level of the at least one pin indicates that the host device provides an extended power budget while the host device is in a standby mode; and

a controller, which is coupled to receive the signal from the sensing circuit and is configured to cause the computing device, in response to the signal, to operate in accordance with an extended operational capability of the host device that is indicated by the floating of the at least one pin.

33. The device according to claim 32, wherein the sensing circuit is configured to detect that the at least one pin is floating.

34. The device according to claim 32, wherein the controller is a network interface controller (NIC), which is configured to provide a wake-on-LAN (WOL) service to the host device using electrical power provided by the extended power budget.

35. The device according to claim 32, wherein the electrical level of the at least one pin indicates that the host device has an extended communication capability.

36. A computing device, comprising:

a bus interface, which is configured to connect the computing device to a host device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins, and which comprises a sensing circuit, which is coupled to detect an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pin and to output a signal in response to the electrical level; and

a controller, which is coupled to receive the signal from the sensing circuit and is configured to cause the computing device, in response to the signal, to operate in accordance with an extended operational capability of the host device that is indicated by the floating of the at least one pin,

wherein the electrical level of the at least one pin indicates that the host device has an extended communication capability, and

wherein the extended communication capability comprises support, via the bus, for a Network Communications Services Interface (NCSI) that is not provided by the standard, and wherein the controller is configured to communicate with a service processor in the host device via the bus using the NCSI.