Methods and systems for replaceable synaptic weight storage in neuro-processors

• US 8,676,734 B2
• Filed: 07/07/2010
• Issued: 03/18/2014
• Est. Priority Date: 07/07/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Aparin, Vladimir
• Primary Examiner(s): Gaffin, Jeffrey A
• Assistant Examiner(s): Sugent, James F
• Application Number:
  US12/831,484
• Publication Number:
  US 20120011087A1
• Time in Patent Office: 1,350 Days
• Field of Search: 706/25, 706/43
• US Class Current: 706/25
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

Certain embodiments of the present disclosure support techniques for storing synaptic weights separately from a neuro-processor chip into a replaceable storage. The replaceable synaptic memory gives a unique functionality to the neuro-processor and improves its flexibility for supporting a large variety of applications. In addition, the replaceable synaptic storage can provide more choices for the type of memory used, and might decrease the area and implementation cost of the overall neuro-processor chip.

Claims

1. An electrical circuit, comprising:

a neuro-processor chip with a plurality of neuron circuits and at least one synapse, wherein the at least one synapse connects a pair of neuron circuits;

a non-volatile removable memory connected to the neuro-processor chip storing weights of the at least one synapse, wherein the weights define, at least in part, a function of the neuro-processor chip, wherein the weights are trained for the pair of neuron circuits before being stored in the non-volatile removable memory, values of the trained weights are replicated and stored in another non-volatile removable memory connected to another neuro-processor chip, and the other neuro-processor chip executes the function of the neuro-processor chip based at least in part on the values of the weights, wherein the non-volatile removable memory is connected to the neuro-processor chip via an interface circuit separate from the removable memory; and

wherein, the non-volatile removable memory is replaced with a second another non-volatile removable memory that stores different values of the weights than the removable memory, and the different values of the weights define, at least in part, another function of the neuro-processor chip.

2. The electrical circuit of claim 1, wherein

the interface circuit carries the weights from the neuro-processor chip to the non-volatile removable memory and from the non-volatile removable memory to the neuro-processor chip.

3. The electrical circuit of claim 1, wherein the neuro-processor chip comprises a local memory for storing at least a portion of the weights.

4. A method for implementing a neural system, comprising:

connecting a non-volatile removable memory to a neuro-processor chip;

training synapse weights for two neuron circuits of a plurality of neuron circuits of the neuro-processor chip;

storing the trained synapse weights on the non-volatile removable memory, wherein a synapse connects the two of the plurality of neuron circuits of the neuro-processor chip, and wherein the weights define, at least in part, a function of the neuro-processor chip;

connecting the non-volatile removable memory to the neuro-processor chip using an interface circuit separate from the non-volatile removable memory;

replicating values of the trained synapse weights to another non-volatile removable memory connected to another neuro-processor chip, wherein the other neuro-processor chip executes the function of the neuro-processor chip based at least in part on the values of the weights; and

replacing the non-volatile removable memory with a second another non-volatile removable memory that stores different values of the weights than the non-volatile removable memory, wherein the different values of the weights define, at least in part, another function of the neuro-processor chip.

5. The method of claim 4, further comprising:

transferring the weights from the neuro-processor chip to the non-volatile removable memory, and from the non-volatile removable memory to the neuro-processor chip, via the interface circuit.

6. The method of claim 4, further comprising:

storing at least a portion of the synapse weights on a local memory within the neuro-processor chip.

7. An apparatus for implementing a neural system, comprising:

means for connecting a non-volatile removable memory to a neuro-processor chip;

means for training synapse weights for two neuron circuits of a plurality of neuron circuits of the neuro-processor chip;

means for storing the trained synapse weights on the non-volatile removable memory, wherein a synapse connects the two of the plurality of neuron circuits of the neuro-processor chip, and wherein the weights define, at least in part, a function of the neuro-processor chip;

means for connecting the non-volatile removable memory to the neuro-processor chip using an interface circuit separate from the non-volatile removable memory;

means for replicating values of the trained weights to another non-volatile removable memory connected to another neuro-processor chip, wherein the other neuro-processor chip executes the function of the neuro-processor chip based at least in part on the values of the weights; and

means for replacing the non-volatile removable memory with a second another non-volatile removable memory that stores different values of the weights than the non-volatile removable memory, wherein the different values of the weights define, at least in part, another function of the neuro-processor chip.

8. The apparatus of claim 7, further comprising:

means for transferring the weights from the neuro-processor chip to the non-volatile removable memory, and from the non-volatile removable memory to the neuro-processor chip, via the interface circuit.

9. The apparatus of claim 7, further comprising:

means for storing at least a portion of the synapse weights on a local memory within the neuro-processor chip.

10. A computer program product for implementing a neural system, comprising a non-transitory computer-readable medium comprising code for:

interfacing a non-volatile removable memory to a neuro-processor chip;

training weights for two neuron circuits of a plurality of neuron circuits of the neuro-processor chip;

storing the trained synapse weights on the non-volatile removable memory, wherein a synapse connects the two of the plurality of neuron circuits of the neuro-processor chip, and wherein the weights define, at least in part, a function of the neuro-processor chip;

connecting the non-volatile removable memory to the neuro-processor chip via an interface circuit separate from the removable memory;

replicating values of the trained weights to another non-volatile removable memory connected to another neuro-processor chip, wherein the other neuro-processor chip executes the function of the neuro-processor chip based at least in part on the values of the weights; and

replacing the non-volatile removable memory with a second another non-volatile removable memory that stores different values of the weights than the non-volatile removable memory, wherein the different values of the weights define, at least in part, another function of the neuro-processor chip.

11. The computer program product of claim 10, wherein the computer-readable medium further comprises code for:

transferring the weights from the neuro-processor chip to the non-volatile removable memory, and from the non-volatile removable memory to the neuro-processor chip, via the interface circuit.

12. The computer program product of claim 10, wherein the computer-readable medium further comprises code for:

storing at least a portion of the synapse weights on a local memory within the neuro-processor chip.