Integrated circuit metal gate structure and method of fabrication

• US 8,679,962 B2
• Filed: 11/04/2008
• Issued: 03/25/2014
• Est. Priority Date: 08/21/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hou, Yong-Tian, Chen, Chien-Hao, Chao, Donald Y., Hung, Cheng-Lung
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US12/264,822
• Publication Number:
  US 20100044806A1
• Time in Patent Office: 1,967 Days
• Field of Search: 438/591, 438/592, 438/588, 257/E21.192, 257/E21.195, 257/E21.201, 257/E21.204, 257/412
• US Class Current: 438/591
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming an interface layer on the semiconductor substrate;

forming a first gate dielectric layer on the interface layer;

forming a first layer on the first gate dielectric layer, wherein the first layer is a metal layer;

oxidizing the first layer to form a metal oxide layer, wherein the oxidizing the metal layer includes gettering oxygen from the interface layer;

forming a second layer including a metal oxide, wherein the forming the second layer includes depositing a layer of at least one of TaC, TaCO, TaCNO and oxidizing the deposited layer using at least one of an anneal and a plasma process, and further includes diffusing oxygen from the second layer to the first gate dielectric layer; and

forming a third layer on the second layer;

wherein the third layer includes metal.

2. The method of claim 1, wherein the oxidizing further includes gettering oxygen from the first gate dielectric layer.

3. The method of claim 1, wherein the interface layer includes silicon oxide.

4. The method of claim 1, wherein the metal oxide layer forms a second gate dielectric layer.

5. The method of claim 4, wherein the second gate dielectric has a dielectric constant greater than the first gate dielectric.

6. The method of claim 1, wherein the oxidizing the first layer to form a metal oxide layer includes a rapid thermal anneal (RTA) process.

7. The method of claim 1, wherein the first layer is selected from the group consisting of Ti, Ta, Hf, Zr, W, TiN, and TaN.

8. The method of claim 1, wherein the first layer is at least one of an elemental metal layer or a metal-rich nitride layer.

9. The method of claim 1 wherein the third layer is a work function metal.

14. The method of claim 1, wherein the first layer is selected from the group consisting of carbon-rich TaC, TaCO, TaCNO, TaN, MoON, TiON, and combinations thereof.

10. A method of semiconductor device fabrication, comprising:

providing a semiconductor substrate;

forming an interfacial layer on the semiconductor substrate;

depositing a high-k dielectric layer on the interfacial layer;

forming a multi-layer metal gate on the high-k dielectric layer, wherein the multi-layer metal gate includes;

forming a first layer, wherein the first layer includes an oxygen gettering composition selected from the group consisting of TaC, TaCO, TaCNO, TaN, TiON, and MoON;

gettering oxygen from the interfacial layer using the first layer;

forming a second layer in-situ with the forming the first layer, wherein the second layer has a composition which includes a metal and oxygen;

oxidizing the second layer to form a metal oxide layer;

diffusing oxygen from the oxidized second layer to the high-k dielectric layer; and

forming a third metal layer.

11. The method of claim 10, wherein the first layer includes a metal-rich nitride.

12. The method of claim 10, third metal is selected from the group consisting of N-rich TiN, N-rich TaN, C-rich TaC, and combinations thereof.

13. The method of claim 10, further comprising:

diffusing oxygen from second layer to the high-k dielectric layer, wherein the second layer is a metal oxide.

15. The method of claim 10, wherein the first layer is selected from the group consisting of TiN, TiSiN, TaC, and combinations thereof.