Reconfiguring a secure system

• US 8,683,191 B2
• Filed: 10/31/2012
• Issued: 03/25/2014
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Datta, Sham M., Kumar, Mohan J., Brickell, Ernie, Schoinas, Ioannis T., Sutton, James A.
• Primary Examiner(s): Zand, Kambiz
• Assistant Examiner(s): Tran, Tongoc
• Application Number:
  US13/664,930
• Publication Number:
  US 20130103938A1
• Time in Patent Office: 510 Days
• Field of Search: 713/1.2, 713/100, 713/165, 713/1, 713/2, 713/10, 713/320, 726/1, 726/22, 711150-152, 711/163, 711/164
• US Class Current: 713/100
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Claims

1. A processor comprising:

a plurality of cores; and

a configuration unit including;

a configuration storage to store configuration information;

a lock to lock the configuration storage;

a lock enable logic to enable the lock during secure system operation in response to a lock enable indicator of a lock enable control field being of a first state, wherein the lock enable logic cannot be reconfigured while the lock is enabled;

logic to determine whether an instruction that generates a configuration write transaction is from sub-operating mode code; and

a lock override logic to override the lock to enable a write to the configuration storage during the secure system operation if the instruction that generates the configuration write transaction is from the sub-operating mode code.

2. The processor of claim 1, further comprising a base storage location to store a base address, where the base address is to specify a first memory address region at which the sub-operating mode code is to be accessed.

3. The processor of claim 1, wherein the sub-operating mode code is system management mode code, further comprising a base storage location to store a base address, where the base address is to specify a first memory address region at which the system management mode code is to be accessed.

4. The processor of claim 1, further comprising determination logic to determine whether the sub-operating mode code is being executed.

5. The processor of claim 1, wherein the sub-operating mode code is system management mode code, further comprising determination logic to determine whether system management mode code is being executed.

6. The processor of claim 5, further comprising address comparison logic to determine whether the system management code is being executed by comparison of an address associated with the instruction to a base address stored in a base storage location.

7. The processor of claim 1, wherein the write to the configuration storage is to cause a reconfiguration to replace a core with a spare core.

8. The processor of claim 7, wherein the replaced core comprises a malfunctioned core.

9. A method comprising:

storing configuration information for a system in a configuration storage of a processor;

enabling a lock with a lock enable logic of the processor to lock the configuration storage during secure system operation in response to a lock enable indicator being of a first state, wherein the lock enable logic cannot be reconfigured while the lock is enabled;

determining whether an instruction that initiates a configuration write transaction is from sub-operating mode code; and

overriding the lock to enable a write to the configuration storage during the secure system operation if the instruction is from the sub-operating mode code.

10. The method of claim 9, further comprising allowing the configuration write transaction in response to determining that the instruction is from the sub-operating mode code.

11. The method of claim 9, further comprising blocking the configuration write transaction in response to determining that the instruction is not from the sub-operating mode code.

12. The method of claim 9, further comprising entering a secure system environment before determining whether the instruction is from the sub-operating mode code.

13. The method of claim 9, further comprising comparing an address associated with the instruction to a base address to determine if the instruction is from the sub-operating mode code.

14. The method of claim 13, further comprising reading the base address from a base address storage location.

15. The method of claim 9, wherein the sub-operating mode is system management mode.

16. A system comprising:

a processor including a plurality of cores and a configuration unit, the configuration unit including;

a configuration storage to store information for the processor;

a lock to lock the configuration storage;

a lock enable logic including a lock enable field to store a lock enable indicator of a first state to enable the lock during secure system operation, wherein the lock enable logic cannot be reconfigured while the lock is enabled;

logic to determine whether an instruction that generates a configuration write transaction is from sub-operating mode code;

a lock override logic to override the lock if the logic determines that the instruction that generates the configuration write transaction is from the sub-operating mode code; and

a dynamic random access memory to store the sub-operating mode code.

17. The system of claim 16, further comprising a chipset coupled to the processor, the chipset comprising:

a second configuration storage to store information for the chipset;

a second lock to lock the second configuration storage;

a second lock enable logic including a lock enable field to store a lock enable indicator of a first state to enable the second lock during the secure system operation, wherein the second lock enable logic cannot be reconfigured while the second lock is enabled;

second logic to determine whether an instruction that generates a configuration write transaction is from the sub-operating mode code; and

a second lock override logic to override the second lock if the second logic determines that the instruction that generates the configuration write transaction is from the sub-operating mode code.

18. The system of claim 17, wherein the system comprises a trusted partition including the processor, a secure virtual machine monitor (SVMM), and a trusted kernel, and an untrusted partition including an untrusted kernel.

19. The system of claim 16, wherein the write to the configuration storage is to cause a reconfiguration to replace a core with a spare core.

20. The system of claim 19, wherein the replaced core comprises a malfunctioned core.