Page based management of flash storage

• US 8,688,894 B2
• Filed: 09/03/2009
• Issued: 04/01/2014
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Pioneer Chip Technology, Ltd.
• Original Assignee: Pioneer Chip Technology, Ltd.
• Inventors: Kuehne, Reinhard
• Primary Examiner(s): LO, KENNETH M
• Application Number:
  US12/584,299
• Publication Number:
  US 20110055458A1
• Time in Patent Office: 1,671 Days
• Field of Search: 711/103, 711/114, 711/207
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

Methods and circuits for page based management of an array of Flash RAM nonvolatile memory devices provide paged base reading and writing and block erasure of a flash storage system. The memory management system includes a management processor, a page buffer, and a logical-to-physical translation table. The management processor is in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected pages, erasing selected blocks, and reading selected pages of the array of nonvolatile memory devices.

Claims

1. A data storage system comprising:

an array of nonvolatile memory devices comprising multiple blocks of sub-arrays that are comprising a plurality of sub-blocks where each sub-block comprises a plurality of sectors and each sector comprising a plurality of bytes of memory cells;

a management processor in communication with the array of nonvolatile memory devices to provide control signals for programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices;

a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing data that is read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor;

a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer;

an input/output adapter connected between an external port and the sub-block buffer and the management processor to receive a logical address, control, and sectors of data encoded in a communication format and translating the logical address, control, and data encoded in the communication format to a format acceptable by the array of nonvolatile memory devices;

a physical address decoder in communication with the input/output adapter to receive the logical address, in communication with the logical-to-physical translation table to transmit the logical address to the logical-to-physical translation table and receive a physical address from the logical-to-physical translation table, and in communication with the management processor to identify that a requested sub-block of data is resident in the sub-block buffer or the array of nonvolatile memory devices; and

sub-block buffer cache table in communication with the management processor and comprising a physical sub-block number identifying a physical location within the array of nonvolatile memory devices associated with a sub-block location within the sub-block buffer, a cache type entry designating a cache type occupied by the physical location, and a status entry classifying the sectors of the sub-block according to a validity status.

2. The data storage system of claim 1 wherein the sub-block is a page, a super-page composed of single blocks within multiple arrays of nonvolatile memory devices, or super page composed of multiple pages with a block.

3. The data storage system of claim 1 wherein the cache types comprise a read cache, streaming cache, write cache, and free list.

4. The data storage system of claim 1 further comprising a least-recently-used table comprising chaining pointers for determining a least recently used sub-block of data resident in the sub-block buffer.

5. The data storage system of claim 4 where during an eviction process of the sub-block buffer by the management processor, the least recently used sub-block of data resident in the sub-block buffer is evicted from the sub-block buffer and written to its designated sub-block within the array of nonvolatile memory devices and the sub-block location within the sub-block buffer is added to the free list of the sub-block buffer cache table.

6. The data storage system of claim 1 further comprising an invalid sub-block table indicating which sub-blocks with selected block of the array of nonvolatile memory devices are valid.

7. The data storage system of claim 1 further comprising a physical-to-logical table for mapping the physical location of the array of nonvolatile memory devices to the logical location wherein an illegal sub-block number indicates that the physical location is erased or invalid.

8. The data storage system of claim 1 further comprising an erase count table in communication with the management processor to maintain an erase count for each block of the array of nonvolatile memory devices.

9. The data storage system of claim 1 further comprising a physical block chain table in communication with the management processor and comprising a linked listing containing pointers for each block of the array of nonvolatile memory devices containing an anchor pointer defining the number of invalid sub-blocks within the block.

10. The data storage system of claim 8 wherein during a garbage collection process of the array of nonvolatile memory devices executed by the management processor, the anchor pointer indicates the block of the array of nonvolatile memory devices having the highest number of invalid sub-blocks and thus permits selection of the block with the highest number of invalid sub-blocks for erasure.

11. The data storage system of claim 10 wherein during a wearleveling process an erased block has its erasure count compared to a maximum count and if the maximum count is exceeded, a block having a lowest erased count is selected and all valid sub-blocks are copied to the low order sub-blocks of the erased block, the block with the lowest erase count is erased, and the newly erased block has its erasure count incremented and it becomes a new spare block available for writing.

12. A memory management circuit for sub-block based reading and writing and block erasure of a flash storage system, wherein the memory management circuit comprises:

a management processor in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices;

a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing data that are read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor;

a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer;

an input/output adapter connected between an external port and the sub-block buffer and the management processor to receive a logical address, control, and sectors of data encoded in a communication format and translating the logical address, control, and data encoded in the communication format to a format acceptable by the array of nonvolatile memory devices;

a physical address decoder in communication with the input/output adapter to receive the logical address, in communication with the logical-to-physical translation table to transmit the logical address to the logical-to-physical translation table and receive a physical address from the logical-to-physical translation table, and in communication with the management processor to identify that a requested sub-block of data is resident in the sub-block buffer or the array of nonvolatile memory devices; and

a sub-block buffer cache table in communication the management processor and comprising a physical sub-block number identifying a physical location within the array of nonvolatile memory devices associated with a sub-block location within the sub-block buffer, a cache type entry designating a cache type occupied by the physical location, and a status entry classifying the sectors of the sub-block according to a validity status.

13. The memory management circuit of claim 12 wherein the sub-block is a page, a super-page composed of single blocks within multiple arrays of nonvolatile memory devices, or super page composed of multiple pages with a block.

14. The memory management circuit of claim 12 wherein the cache types comprise a read cache, streaming cache, write cache, and free list.

15. The memory management circuit of claim 12 further comprising a least-recently-used table comprising chaining pointers for determining a least recently used sub-block of data resident in the sub-block buffer.

16. The memory management circuit of claim 15 where during an eviction process of the sub-block buffer by the management processor, the least recently used sub-block of data resident in the sub-block buffer is evicted from the sub-block buffer and written to its designated sub-block within the array of nonvolatile memory devices and the sub-block location within the sub-block buffer is added to the free list of the sub-block buffer cache table.

17. The memory management circuit of claim 13 further comprising an invalid sub-block table indicating which sub-blocks with selected block of the array of nonvolatile memory devices are valid.

18. The memory management circuit of claim 13 further comprising a physical-to-logical table for mapping the physical location of the array of nonvolatile memory devices to the logical location wherein an illegal sub-block number indicates that the physical location is erased or invalid.

19. The memory management circuit of claim 13 further comprising an erase count table in communication with the management processor to maintain an erase count for each block of the array of nonvolatile memory devices.

20. The memory management circuit of claim 13 further comprising a physical block chain table in communication with the management processor and comprising a linked listing containing pointers for each block of the array of nonvolatile memory devices containing an anchor pointer defining the number of invalid sub-blocks within the block.

21. The memory management circuit of claim 19 wherein during a garbage collection process of the array of nonvolatile memory devices executed by the management processor, the anchor pointer indicates the block of the array of nonvolatile memory devices having the highest number of invalid sub-blocks and thus permits selection of the block with the highest number of invalid sub-blocks for erasure.

22. The memory management circuit of claim 21 wherein during a wearleveling process an erased block has its erasure count compared to a sliding window erase count and if the sliding window erase count is exceeded, a block having a lowest block erase count is selected and all valid sub-blocks are copied to the low order sub-blocks of the erased block, the block with the lowest block erase count is erased, and the newly erased block has its erasure count incremented and it becomes a new spare block available for writing.

23. The memory management circuit of claim 22 wherein during the wearleveling process the sliding window erase count is calculated as the lowest block erase count plus a block erase count threshold value.