Hardware-accelerated lossless data compression
First Claim
1. A data compression apparatus, comprising:
- a plurality of hash memories each associated with a different lane of a plurality of lanes, and each lane comprising data bytes of an incoming data stream being received by the data compression apparatus;
validity table comprising array elements each comprising a plurality of validity bits, wherein each validity bit within an array element corresponds to a different lane of the plurality of lanes;
control logic, coupled to the plurality of hash memories and the validity table, that initiates a read of a hash memory entry if a validity bit that corresponds to the lane associated with the hash memory entry indicates that said hash memory entry is valid; and
an encoder, coupled to the plurality of hash memories and the control logic, that compresses at least the data bytes for the lane associated with the hash memory comprising the valid hash entry if said valid hash entry comprises data that matches the data bytes for the lane.
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Abstract
Systems for hardware-accelerated lossless data compression are described. At least some embodiments include data compression apparatus that includes a plurality of hash memories each associated with a different lane of a plurality of lanes (each lane including data bytes of a data unit being received by the compression apparatus), an array including array elements each including a plurality of validity bits (each validity bit within an array element corresponding to a different lane of the plurality of lanes), control logic that initiates a read of a hash memory entry if a corresponding validity bit indicates that said entry is valid, and an encoder that compresses at least the data bytes for the lane associated with the hash memory comprising the valid entry if said valid entry comprises data that matches the lane data bytes.
67 Citations
19 Claims
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1. A data compression apparatus, comprising:
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a plurality of hash memories each associated with a different lane of a plurality of lanes, and each lane comprising data bytes of an incoming data stream being received by the data compression apparatus; validity table comprising array elements each comprising a plurality of validity bits, wherein each validity bit within an array element corresponds to a different lane of the plurality of lanes; control logic, coupled to the plurality of hash memories and the validity table, that initiates a read of a hash memory entry if a validity bit that corresponds to the lane associated with the hash memory entry indicates that said hash memory entry is valid; and an encoder, coupled to the plurality of hash memories and the control logic, that compresses at least the data bytes for the lane associated with the hash memory comprising the valid hash entry if said valid hash entry comprises data that matches the data bytes for the lane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data compression method performed by a compression engine, the data compression method comprising:
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associating a plurality of hash memories each with a different lane of a plurality of lanes, each lane comprising data bytes of an incoming data stream being received by a compression apparatus; storing a plurality of validity bits within each of a plurality of array elements, wherein each validity bit within an array element corresponds to a different lane of the plurality of lanes; initiating a read of a hash memory entry if a validity bit that corresponds to the lane associated with the hash memory entry indicates that said hash memory entry is valid; and compressing at least the data bytes for the lane associated with the hash memory comprising the valid hash memory entry if said valid hash memory entry comprises data that matches the data bytes for the lane. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification