Retargeting of a write operation retry in the event of a write operation failure

• US 8,694,714 B2
• Filed: 01/18/2008
• Issued: 04/08/2014
• Est. Priority Date: 01/18/2008
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Kern, William, Chan, Peter
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Ayash, Marwan
• Application Number:
  US12/016,674
• Publication Number:
  US 20090187700A1
• Time in Patent Office: 2,272 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer.

Claims

1. A memory system for providing non-volatile write operation retry, comprising:

a first flash memory configured to receive write data content and attempt to write the write data content to a memory block of a plurality of memory blocks, in response to the attempt being unsuccessful, store the write data content that is associated with a failed write operation to an internal buffer within the first flash memory that is differentiated from the plurality of blocks and, retain the write data content for one or more write operation retries on the internal buffer of the first flash memory; and

a volatile memory comprising write operation retry logic that is configured to receive notice of the failed write operation from the first flash memory and command a first write operation retry of the one or more write operation retries to the first flash memory by issuing a write operation command to the first flash memory that commands the first flash memory to use the internal buffer of the first flash memory as a source of the write data content for the first write operation retry,

wherein the write operation retry logic commands the first write operation retry only after a preconfigured sequential series of retry processes are executed, and the write operation retry logic is further configured to execute a first determination as to whether a retry process determining logic is employed to logically execute a second determination as to which one of two or more retry logics for different retry options attempt the first write operation retry based on pre-existing conditions.

2. The memory system of claim 1, wherein the write operation retry logic is further configured to provide a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address of the first flash memory upon receiving the retarget address and the write operation command.

3. The memory system of claim 1, wherein the write operation retry logic is further configured to transfer the write data content to a different buffer of a second flash memory from the internal buffer of the first flash memory.

4. The memory system of claim 3, wherein the write operation retry logic is further configured to issue a read command to the first flash memory and issue a write command to the second flash memory.

5. The memory system of claim 1, wherein the write operation retry logic is further configured to command a second write operation retry based on the write data content, if the first write operation retry is unsuccessful.

6. The memory system of claim 5, wherein the write operation retry logic is further configured to command the first write operation retry to provide a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address of the first flash memory in response to the failed write operation and attempts a second write operation retry-operable to transfer the write data content to a different buffer of a second flash memory upon receiving the write operation command and the retarget address when the first write operation retry is unsuccessful.

7. The memory system of claim 5, wherein the write operation logic is further configured to command the first write operation retry to transfer the write data content associated with the failed write operation to a second flash memory in response to the failed write operation to the first flash memory and to command the second write operation retry based on the write data content, if the first write operation retry is unsuccessful, to provide a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address of the first flash memory.

8. The memory system of claim 1, wherein the write operation logic is further configured to select a write operation retry type from at least one of a first retry type comprising providing a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address of the first flash memory or a second retry type comprising transferring the write data content to a second flash memory.

9. The memory system of claim 1, wherein the internal buffer comprises a NAND page buffer.

21. The memory system of claim 3, wherein the volatile memory further comprises a data transfer protocol that is configured to issue a read command to the buffer of the first flash memory, subsequently issue a write command to the different buffer of the second flash memory, and facilitate transfer of the write data content between the buffer and the different buffer with a temporary storage of the volatile memory.

10. A method for retrying a write operation on a flash memory in a computing system, comprising:

retaining write data content in an internal buffer of a first flash memory after a failed write operation;

receiving notice of a failed write operation of write data content from the first flash memory; and

attempting a first write operation retry of the write data content without re-transferring the write data content to the internal buffer of the first flash memory and obtaining the write data content from the internal buffer of the first flash memory that is configured to be a source of the write data content used in the first write operation retry only after a preconfigured sequential series of retry processes are executed; and

executing a first determination as to whether a retry process determining logic is employed to logically execute a second determination as to which one of two or more retry logics for different retry options attempt the first write operation retry based on pre-existing conditions.

11. The method of claim 10, wherein attempting the first write operation retry further comprises providing a retarget address to the first flash memory and a write operation command, wherein the first flash memory is configured to write the write data content to the retarget address to the first flash memory, upon receiving the retarget address and the write operation command.

12. The method of claim 10, wherein attempting the first write operation retry further comprises transferring the write data content to a different buffer of a second flash memory from the internal buffer of the first flash memory.

13. The method of claim 12, wherein transferring the write data content to the second flash memory further comprises issuing a read command to the first flash memory and issuing a write command to the second flash memory.

14. The method of claim 10, further comprising attempting a second write operation retry based on the write data content, if the first write operation retry is unsuccessful.

15. The method of claim 14, wherein attempting the first write operation retry further comprises providing a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address and attempting the second write operation retry further comprises transferring the write data content to a different buffer of a second flash memory.

16. The method of claim 14, wherein attempting the first write operation retry further comprises transferring the write data content to a different buffer of a second flash memory and attempting the second write operation retry further comprises providing a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the second flash memory with the retarget address.

17. The method of claim 10, wherein attempting the first write operation retry further comprises logically selecting a write operation retry type from at least one of a first retry type comprising providing a retarget address to the first flash memory, wherein the first flash memory attempts to write the write data content to the retarget address or a second retry type comprising transferring the write data content to a second flash memory.

18. The method of claim 10, further comprising attempting a second write operation retry based on data stored in a system retry buffer, if the first write operation retry is unsuccessful.

19. A method for performing a write operation on a flash memory to facilitate a write operation retry, comprising:

obtaining write data content associated with a write operation on the flash memory;

storing the write data content to a page buffer internal to the flash memory;

attempting to store the write data content to a first address, specified in the write operation, of the flash memory;

retaining the write data content in the page buffer when the attempt to store the write data content to the first address fails; and

attempting a write operation retry with the write data content retained in the page buffer after a preconfigured sequential series of retry processes are executed the to store the write data content to the first address fails, and without any re-transferring of the write data content from outside the flash memory to the page buffer; and

executing a first determination as to whether a retry process determining logic is employed to logically execute a second determination as to which one of two or more retry logics for different retry options attempt the first write operation retry based on pre-existing conditions.

20. The method of claim 19, wherein attempting the write operation retry comprises:

receiving a retarget address; and

attempting to store the write data content retained in the page buffer to the retarget address of the flash memory.