Delay line calibration

• US 8,698,572 B2
• Filed: 12/14/2010
• Issued: 04/15/2014
• Est. Priority Date: 11/15/2006
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Chong U., Julian, David Jonathan, Ekbal, Amal
• Primary Examiner(s): Takaoka, Dean O
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US12/967,216
• Publication Number:
  US 20110080203A1
• Time in Patent Office: 1,218 Days
• Field of Search: 333/18, 333/138, 333/139, 327/158, 327/279
• US Class Current: 333/18
• CPC Class Codes: H03K 2005/00104 using a reference signal, e.g. a reference clock
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Claims

1. An apparatus for signal processing, comprising:

a delay line having a delay that is adapted to be adjusted in accordance with a control signal;

a feedback path adapted to couple an output of the delay line to an input of the delay line;

a counter coupled to the output of the delay line and adapted to generate a count by counting pulse signals outputted by the delay line; and

a controller coupled to an output of the counter and adapted to generate the control signal based on the count.

2. The apparatus of claim 1, further comprising a signal generator adapted to generate at least one seed pulse signal that is fed to the input of the delay line.

3. The apparatus of claim 1, further comprising a signal generator adapted to generate a plurality of seed pulse signals that are fed to the input of the delay line, while the pulses signals are concurrently routed from the output of the delay line through the feedback path.

4. The apparatus of claim 1, wherein:

the feedback path is adapted to feed the pulse signals to the input of the delay line; and

the controller is adapted to compare the count generated by the counter with an expected count.

5. The apparatus of claim 4, wherein the controller is adapted to generate the control signal based on a difference between the count and the expected count.

6. The apparatus of claim 4, wherein the controller is adapted to adjust the expected count or the count to compensate for a component delay in the feedback path.

7. The apparatus of claim 6, wherein the controller is adapted to compensate for the component delay in accordance with a statistical mean associated with the component delay.

8. The apparatus of claim 1, wherein the feedback path comprises an amplifier adapted to provide gain in the feedback path.

9. The apparatus of claim 8, further comprising a pulse detector adapted to generate a gain control signal in accordance with an amplitude of at least one of the pulse signals outputted by the delay line, wherein the amplifier is adapted to adjust the gain in the feedback path in accordance with the gain control signal.

10. The apparatus of claim 1, wherein the feedback path comprises a pulse regenerator.

11. The apparatus of claim 10, wherein the pulse regenerator comprises a matched filter.

12. A method of signal processing, comprising:

coupling pulse signals outputted by a delay line to an input of the delay line using a feedback path;

counting the pulse signals outputted by the delay line;

adjusting a delay of the delay line based on the counting; and

generating seed pulse signals and feeding the seed pulse signals to the input of the delay line, while concurrently routing the pulse signals outputted by the delay line through the feedback path.

13. The method of claim 12, wherein adjusting the delay further comprises comparing an expected count with a count generated by the counting.

14. The method of claim 13, wherein adjusting the delay further comprises adjusting the delay by an amount that is related to a difference between the count and the expected count.

15. A method of signal processing, comprising:

coupling pulse signals outputted by a delay line to an input of the delay line;

counting the pulse signals outputted by the delay line;

adjusting a delay of the delay line based on the counting, wherein adjusting the delay further comprises comparing an expected count with a count generated by the counting; and

adjusting the expected count or the count to compensate for a component delay in a feedback path.

16. The method of claim 15, wherein the expected count or the count is adjusted according to a statistical mean associated with the component delay.

17. A method of signal processing, comprising:

coupling pulse signals outputted by a delay line to an input of the delay line;

counting the pulse signals outputted by the delay line;

adjusting a delay of the delay line based on the counting; and

adjusting a gain of the pulse signals coupled to the input of the delay line.

18. The method of claim 17, wherein the gain is based on a detection of at least a portion of the pulse signals outputted by the delay line.

19. A method of signal processing, comprising:

coupling pulse signals outputted by a delay line to an input of the delay line;

counting the pulse signals outputted by the delay line;

adjusting a delay of the delay line based on the counting; and

regenerating the pulse signals and wherein coupling the pulse signals to the input of the delay line comprises coupling the regenerated pulse signals to the input of the delay line.

20. The method of claim 19, wherein regenerating the pulse signals comprises performing a matched filter operation on the pulse signals.

21. An apparatus for signal processing, comprising:

means for coupling pulse signals outputted by a signal delaying means to an input of the signal delaying means;

means for counting the pulse signals outputted by the signal delaying means;

means for adjusting a delay of the signal delaying means based on the counting, wherein adjusting the delay further comprises comparing an expected count with a count generated by the means for counting; and

means for adjusting the expected count or the count to compensate for a component delay in a feedback path.

22. A computer-program product, comprising:

a non-transitory computer-readable storage medium encoded with codes for causing an apparatus to;

couple pulse signals outputted by a delay line to an input of the delay line;

generate a count of the pulse signals outputted by the delay line;

adjusting a delay of the delay line based on the count, wherein adjusting the delay further comprises comparing an expected count with the generated count; and

adjusting the expected count or the count to compensate for a component delay in a feedback path.