Timing phase detection using a matched filter set
First Claim
1. A method for utilizing data decoding circuitry to determine clock phase, the method comprising:
- providing a matched filter bank, wherein the matched filter bank is operable to receive a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence;
receiving a timing pattern;
re-tuning the first matched filter to detect a first pattern corresponding to the timing pattern sampled using a first phase of the sample clock; and
re-tuning the second matched filter to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock.
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Abstract
Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.
104 Citations
20 Claims
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1. A method for utilizing data decoding circuitry to determine clock phase, the method comprising:
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providing a matched filter bank, wherein the matched filter bank is operable to receive a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence; receiving a timing pattern; re-tuning the first matched filter to detect a first pattern corresponding to the timing pattern sampled using a first phase of the sample clock; and re-tuning the second matched filter to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A timing phase adjustment circuit, the circuit comprising:
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a bank of matched filters, wherein the bank of matched filters includes a first matched filter tuned to detect a first pattern corresponding to a timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock; and a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter. - View Dependent Claims (12, 13, 14, 15)
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16. A communication system including a receiver with a phase timing adjustment circuit, the system comprising:
a receiver, wherein the receiver includes; an analog to digital converter operable to receive an analog input and to provide a series of digital samples synchronous to a sample clock, and wherein the series of digital samples correspond to a timing pattern; a bank of matched filters, wherein the bank of matched filters is operable to receive the series of digital samples, wherein the bank of matched filters includes a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock; and a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter. - View Dependent Claims (17, 18, 19, 20)
Specification