Transistor and display device

• US 8,710,499 B2
• Filed: 02/19/2013
• Issued: 04/29/2014
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sasaki, Toshinari, Sakata, Junichiro, Tsubuku, Masashi
• Primary Examiner(s): MONTALVO, EVA Y
• Application Number:
  US13/770,120
• Publication Number:
  US 20130153910A1
• Time in Patent Office: 434 Days
• Field of Search: 257/72, 257/43, 257/258, 257/83, 257/84, 257/88, 257/E29.596
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Claims

1. A transistor comprising:

a gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with a gate insulating layer therebetween;

a source electrode layer adjacent to the oxide semiconductor layer with an oxide conductive layer therebetween; and

a drain electrode layer adjacent to the oxide semiconductor layer with the oxide conductive layer therebetween,

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200°

C. and less than or equal to 350°

C.

2. The transistor according to claim 1, wherein the oxide semiconductor layer is amorphous.

3. The transistor according to claim 1, wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

4. The transistor according to claim 1, further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

5. The transistor according to claim 4, wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

6. The transistor according to claim 1, wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.

7. A transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide conductive layer over the oxide semiconductor layer;

a source electrode layer over the oxide conductive layer; and

a drain electrode layer over the oxide conductive layer;

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200°

C. and less than or equal to 350°

C.

8. The transistor according to claim 7, wherein the oxide semiconductor layer is amorphous.

9. The transistor according to claim 7, wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

10. The transistor according to claim 7, further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

11. The transistor according to claim 10, wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

12. The transistor according to claim 7, wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.

13. A display device comprising:

a pixel portion over a substrate; and

a driver circuit over the substrate and comprising a transistor;

the transistor comprising;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide conductive layer over the oxide semiconductor layer;

a source electrode layer over the oxide conductive layer; and

a drain electrode layer over the oxide conductive layer;

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200°

C. and less than or equal to 350°

C.

14. The transistor according to claim 13, wherein the oxide semiconductor layer is amorphous.

15. The transistor according to claim 13, wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

16. The transistor according to claim 13, further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

17. The transistor according to claim 16, wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

18. The transistor according to claim 13, wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.