Apparatus and method for multiplying frequency of a clock signal

• US 8,710,879 B2
• Filed: 07/06/2012
• Issued: 04/29/2014
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan), Silicon Integrated Systems Corporation USA (Silicon Integrated Systems Corporation Taiwan)
• Original Assignee: Silicon Integrated Systems Corporation USA (Silicon Integrated Systems Corporation Taiwan)
• Inventors: Lin, Song Sheng
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US13/543,350
• Publication Number:
  US 20140009193A1
• Time in Patent Office: 662 Days
• Field of Search: 327/113, 327/115, 327/116
• US Class Current: 327/115
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Claims

1. A method for multiplying frequency of a clock signal, comprising:

providing an initial oscillator signal;

via a control signal generation circuit, comparing the initial oscillator signal with a reference signal to generate a first control signal and output the first control signal to a threshold value generation circuit;

via the threshold value generation circuit, selecting one of at least one lower threshold value and at least one upper threshold value according to at least the first control signal, and outputting the selected one of the at least one upper and lower threshold values to a digital and logical module; and

via the digital and logical module, processing a comparison between the initial oscillator signal and the selected one of the at least one upper and lower threshold values and a comparison between the initial oscillator signal and a low level signal, so as to output an output clock signal, wherein the step of outputting the output clock signal comprises;

generating a plurality of logic signals by a plurality of comparators comparing the initial oscillator signal with the selected one of the at least one upper and lower threshold values and comparing the initial oscillator signal with the low level signal; and

processing the logic signals by the digital and logical module to output the output clock signal;

wherein while one of the logic signals is updated by the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values, at least other one of the logic signals is updated by the comparison between the initial oscillator signal and the low level signal.

2. The method for multiplying frequency of a clock signal according to claim 1, further comprising:

calibrating the at least one lower threshold value and the at least one upper threshold value by the threshold value generation circuit, comprising;

detecting duty cycles or pulse width of the logic signals; and

adjusting the at least one upper threshold value and/or the at least one lower threshold value if a duty cycle of at least one of the logic signals is different from a corresponding predefined duty cycle; and

transforming the selected one of the at least one upper and lower threshold values from digital type to analog type and outputting the transformed one of the at least one upper and lower threshold values.

3. The method for multiplying frequency of a clock signal according to claim 2, wherein the step of generating the logic signals comprises:

updating a first logic signal of the logic signals by comparing the initial oscillator signal with the upper threshold value or with the low level signal; and

updating a second logic signal of the logic signals by comparing the initial oscillator signal with the lower threshold value or with the low level signal;

wherein while one of the first and second logic signals is updated by comparing the initial oscillator signal with the corresponding one of the upper and lower threshold values, other one of the first and second logic signals is updated by comparing the initial oscillator signal with the low level signal.

4. The method for multiplying frequency according to claim 2, wherein the at least one lower threshold value comprises a first and a second lower threshold values, the at least one upper threshold value comprises a first and a second upper threshold values, and the step of generating the logic signals comprises:

updating a first logic signal of the logic signals by comparing the initial oscillator signal with the first upper threshold value or with the low level signal;

updating a second logic signal of the logic signals by comparing the initial oscillator signal with the first lower threshold value or with the low level signal;

updating a third logic signal of the logic signals by comparing the initial oscillator signal with the second upper threshold value or with the low level signal; and

updating a fourth logic signal of the logic signals by comparing the initial oscillator signal with the second lower threshold value or with the low level signal;

wherein while one of the logic signals is updated by comparing the initial oscillator signal with the corresponding one of the first and second upper and lower threshold values, other ones of the logic signals are respectively updated by comparing the initial oscillator signal with the low level signal.

5. The method for multiplying frequency of a clock signal according to claim 4, wherein the step of outputting the output clock signal further comprises:

processing the first and third logic signals through a first XNOR gate to output a first sub logic signal;

processing the second and fourth logic signals through a second XNOR gate to output a second sub logic signal; and

processing the first and second sub logic signals through a first NAND gate to output the output clock signal.

6. The method for multiplying frequency of a clock signal according to claim 4, wherein the step of selecting the one of the at least one upper and lower threshold values comprises:

processing a second control signal and the first logic signal to output a first NAND signal through a second NAND gate, wherein the second control signal is generated by inverting the first control signal;

processing the first control signal and the second logic signal through a third NAND gate to output a second NAND signal;

processing the first and second NAND signals through a second NOR gate to output a third control signal; and

decoding the third control signal according to the first control signal to output a selection signal through which the one of the first and second upper and lower threshold values is selected.

7. The method for multiplying frequency of a clock signal according to claim 4, wherein the step of selecting the one of the at least one upper and lower threshold values comprises:

selecting one of the first and second logic signals as a third control signal according to the first control signal; and

decoding the third control signal according to the first control signal to output a selection signal through which the one of the first and second upper and lower threshold values is selected.

8. The method for multiplying frequency of a clock signal according to claim 2, further comprising:

preserving the at least one upper and lower threshold values.

9. An apparatus for multiplying frequency of a clock signal, comprising:

an oscillation circuit, for generating an initial oscillator signal;

a control signal generation circuit, electronically connected to the oscillation circuit, for comparing the initial oscillator signal with a reference signal to generate a first control signal;

a threshold value generation circuit, electronically connected to the oscillation circuit and the control signal generation circuit, for receiving the first control signal and outputting each of at least one upper threshold value and at least one lower threshold value by turns according to at least the first control signal; and

a clock output circuit, electronically connected to the oscillation circuit, the control signal generation circuit and the threshold value generation circuit and comprising a digital and logical module, wherein the digital and logical module processes a comparison between the initial oscillator signal and the outputted one of the at least one upper and lower threshold values and a comparison between the initial oscillator signal and a low level signal to update an output clock signal,

wherein the threshold value generation circuit comprises;

a calibration unit, electronically connected to the oscillation circuit and the clock output circuit, for selectively adjusting the at least one upper threshold value and the at least one lower threshold value; and

a digital to analog converter, for selectively converting the one of the at least one upper and lower threshold values from digital type to analog type and outputting the converted one of the at least one upper and lower threshold values to the clock output circuit.

10. The apparatus for multiplying frequency of a clock signal according to claim 9, wherein the clock output circuit further comprises:

a plurality of comparators, electronically connected to the digital to analog converter and the oscillation circuit, for comparing the initial oscillator signal with the outputted one of the at least one upper and lower threshold values and with at least one low level signal to generate a plurality of logic signals.

11. The apparatus for multiplying frequency of a clock signal according to claim 10, further comprising:

a plurality of S/H circuits, connected to the digital to analog converter and the comparators, for asynchronously providing a path through which the digital to analog converter transmits the outputted one of the at least one upper and lower threshold values to corresponding one of the comparators.

12. The apparatus for multiplying frequency of a clock signal according to claim 11, wherein the control signal generation circuit comprising:

a control comparator, connected to the oscillation circuit, for comparing the initial oscillator signal with the reference signal to output the first control signal; and

an inverter, connected to the control comparator, for inverting the first control signal to output a second control signal.

13. The apparatus for multiplying frequency of a clock signal according to claim 12, wherein the threshold value generation circuit further comprises:

a storage means, connected to the calibration unit and the digital to analog converter, for preserving the upper threshold value and the lower threshold value and selectively outputting one of the preserved upper and lower threshold values to the corresponding one comparator according to the first control signal.

14. The apparatus for multiplying frequency of a clock signal according to claim 10, wherein the comparators comprise a first comparator and a second comparator, the first comparator compares the initial oscillator signal with the upper threshold value or with the low level signal to generate a first logic signal of the logic signals, the second comparator comprises the initial oscillator signal with the lower threshold value or with the low level signal to generate a second logic signal of the logic signals, and

the digital and logical module comprises a NOR gate which processes the first logic signal and the second logic signal to update the output clock signal.

15. The apparatus for multiplying frequency of a clock signal according to claim 10, wherein the at least one upper threshold value comprises a first upper threshold, value and a second upper threshold value, the at least one lower threshold value comprises a first lower threshold value and a second lower threshold value, and the comparators comprise:

a first comparator, for comparing the initial oscillator signal with the first upper threshold value or with the low level signal to generate a first logic signal of the logic signals;

a second comparator, for comparing the initial oscillator signal with the first lower threshold value or with the low level signal to generate a second logic signal of the logic signals;

a third comparator, for comparing the initial oscillator signal with the second upper threshold value or with the low level signal to output a third logic signal of the logic signals; and

a fourth comparator, for comparing the initial oscillator signal with the second lower threshold value or with the low level signal to output a fourth logic signal of the logic signals;

wherein while one of the first, second, third and fourth comparators compares the initial oscillator signal with the corresponding one of the first and second lower and upper threshold values, other ones of the first, second, third and fourth comparators respectively compare the initial oscillator signal with the low level signal.

16. The apparatus for multiplying frequency of a clock signal according to claim 15, wherein the digital and logic module comprises:

a first XNOR, connected to the first and third comparators, for receiving the first and third logic signals to output a first sub logic signal;

a second XNOR, connected to the second and fourth comparators, for receiving the second and fourth logic signals to output a second sub logic signal; and

a first NAND, connected to the first and second XNORs, for receiving the first sub and second sub logic signals to output the output clock signal.

17. The apparatus for multiplying frequency of a clock signal according to claim 15, wherein the threshold value generation circuit further comprises:

a storage means, electrically connected to the calibration unit and the digital and logical converter, for preserving the first and second upper and lower threshold values and selectively outputting one of the preserved first and second upper and lower threshold values to the digital to analog converter according to a selection signal; and

a threshold selection unit, electrically connected to the storage means, the control signal generation circuit and the first and second comparators, for providing the selection signal according to the first and second logic signals and the first control signal.

18. The apparatus for multiplying frequency of a clock signal according to claim 17, wherein the threshold selection unit comprising:

a multiplexer, electrically connected to the first and second comparators and the control signal generation circuit, for selecting one of the first and second logic signals as a third control signal according to the first control signal; and

a decoder, electrically connected to the multiplexer and the control signal generation circuit, for decoding the third control signal according to the first control signal to output the selection signal.

19. The apparatus for multiplying frequency of a clock signal according to claim 17, wherein the threshold selection unit comprising:

a second NAND, electrically connected to the control signal generation circuit and the clock output circuit, for receiving an inverse first logic signal and a second control signal to output a first NAND signal, wherein the inverse first logic signal is generated by inverting the first logic signal, and the second control signal is generated by inverting the first control signal;

a third NAND, electrically connected to the control signal generation circuit and the clock output circuit, for receiving the second logic signal and the first control signal to output a second NAND signal;

a NOR, electrically connected to the second and third NANDs, for receiving the first and second NAND signals to output a third control signal; and

a decoder, electrically connected to the NOR and the control signal generation circuit, for decoding the third control signal according to the first control signal to output the selection signal.

20. The apparatus for multiplying frequency of a clock signal according to claim 10, wherein the threshold value generation circuit calibrates the at least one lower threshold value and the at least one upper threshold value through a calibration procedure, and the calibration procedure comprises:

detecting duty cycles or pulse width of the logic signals; and

adjusting the at least one upper threshold value and/or the at least one lower threshold value if the duty cycle of at least one of the logic signals is different from a corresponding predefined duty cycle.