Method and system for remapping processing elements in a pipeline of a graphics processing unit

• US 8,711,156 B1
• Filed: 09/30/2004
• Issued: 04/29/2014
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Acocella, Dominic, McDonald, Timothy J., Gimby, Robert W., Kong, Thomas H.
• Primary Examiner(s): Tung, Kee M
• Assistant Examiner(s): Liu, Zhengxi
• Application Number:
  US10/956,609
• Time in Patent Office: 3,498 Days
• Field of Search: 345/506, 345/568
• US Class Current: 345/506
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.

Claims

1. A method of remapping processing elements in a pipeline of a graphics processing unit, comprising:

a host of said pipeline of said graphics processing unit receiving graphical input data from a central processing unit;

after said receiving, the host determining a number of enabled processing elements from a plurality of processing elements in said pipeline that perform identical functions, said plurality of processing elements for animating, coloring, and lighting a surface of an image;

a front end receiving said graphical input data from said host, said front end is coupled to said host;

said front end converting said graphical input data to a format compatible with said pipeline of said graphics processing unit;

after said converting, a cache distributor receiving said graphical input data from said front end, said cache distributor is coupled to said front end;

virtually addressing each of said enabled processing elements above a translator to virtually process said graphical input data;

said translator receiving said graphical input data from said cache distributor;

said translator mapping virtual addresses of each of said enabled processing elements to physical addresses of said enabled processing elements in said plurality of processing elements, said mapping comprises using a translation table, said translator is coupled to said cache distributor;

physically processing said graphical input data at said physical addresses of said enabled processing elements, said plurality of processing elements are coupled to said translator; and

physically addressing each of said enabled processing elements below said translator to further process said graphical input data.

2. The method of claim 1, further comprising:

before said receiving said graphical input data, disabling a first processing element by setting a validity fuse corresponding to said first processing element; and

wherein said determining a number of enabled processing elements comprises checking status of a corresponding validity fuse for each of said plurality of processing elements, wherein a set fuse indicates a processing element that is disabled, and an intact fuse indicates an enabled processing element.

3. The method of claim 2, wherein said setting said validity fuse comprises breaking a physical, electrical fuse connection.

4. The method of claim 1, further comprising:

before said receiving said graphical input data, disabling a first processing element through a software override; and

wherein said determining a number of enabled processing elements comprises recognizing said software override that indicates said first processing element is disabled.

5. The method of claim 4, further comprising:

reenabling said first processing element by disengaging said software override.

6. The method of claim 1, wherein said mapping virtual addresses comprises:

mapping virtual representations of cache entries in a cache memory corresponding to said enabled processing elements that are virtualized to physical representations of said cache entries in said cache memory corresponding to said processing elements.

7. The method of claim 6, wherein said mapping is a one-to-one relationship between virtual representations and physical representations of cache entries in said cache memory.

8. The method of claim 6, wherein said mapping virtual addresses further comprises:

load balancing said virtual representations of cache entries between cache entries corresponding to said enabled processing elements.

9. The method of claim 6, wherein said mapping virtual addresses further comprises:

assigning randomly said virtual representations of cache entries between cache entries corresponding to said enabled processing elements.

10. The method of claim 1, wherein said plurality of processing elements comprises a plurality of vertex processing engines (VPE), and said pipeline comprises a vertex pipeline.

11. The method of claim 1, wherein said translator comprises a vertex attribute buffer (VAB).

12. A system for remapping processing elements in a pipeline of a graphics processing unit comprising:

a host of said pipeline for receiving graphical input data from a central processing unit, said host for determining a number of enabled processing elements from a plurality of processing elements in said pipeline that each perform identical functions, said plurality of processing elements for animating, coloring, and lighting a surface of an image;

a front end for receiving said graphical input data from said host, said front end is coupled to said host, said front end for converting said graphical input data to a format compatible with said pipeline of said graphics processing unit;

a cache distributor coupled to receive said graphical input data from said front end, and said cache distributor for assigning said graphical input data to virtual addresses of cache entries in a memory cache that correspond with virtual representations of said enabled processing elements; and

a translator coupled to receive said graphical input data from said cache distributor, and said translator for using a translation table for mapping said virtual addresses of said cache entries to physical addresses of said cache entries that correspond with said enabled processing elements and for processing said graphical input data at said physical addresses of said cache entries, wherein modules below said translator in said pipeline address said physical addresses of said cache entries, said plurality of processing elements are coupled to said translator.

13. The system of claim 12, wherein said plurality of processing elements comprises a plurality of vertex processing engines (VPEs), said pipeline comprises a vertex pipeline, and wherein said translator comprises a vertex attribute buffer (VAB).

14. The system of claim 13, further comprising:

a view port culling module coupled to receive processed graphics data from said plurality of vertex processing engines for performing back face culling;

a color assembly module coupled to receive said processed graphics data that is back faced culled from said view port culling module for assembling color data in said vertex pipeline; and

a setup module coupled to receive said processed graphics data that is back faced culled from said view port culling module for pixelating said processed graphics data.

15. The system of claim 13, wherein said color assembly module is coupled to said host.

16. The system of claim 13, wherein said VAB further comprises a mapper using a mapping table for mapping said virtual addresses of said cache entries to said physical addresses of said cache entries that correspond with said enabled VPEs.

17. The system of claim 13, wherein said cache distributor is for randomly assigning said graphical input data between said virtual and physical addresses of said cache entries corresponding with said enabled VPEs.

18. The system of claim 12, further comprising:

a view port culling module coupled to receive processed graphics data from said plurality of processing elements for performing back face culling.

19. A computer system comprising:

a central processing unit for processing information; and

a computer readable memory coupled to said central processing unit and containing program instructions that implement a method of remapping processing elements in a pipeline of a graphics processing unit, comprising;

a host of said pipeline of said graphics processing unit receiving graphical input data from said central processing unit;

after said receiving, the host determining a number of enabled processing elements from a plurality of processing elements in said pipeline of said graphics processing unit that perform identical functions, said plurality of processing elements for animating, coloring, and lighting a surface of an image;

a front end receiving said graphical input data from said host, said front end is coupled to said host;

said front end converting said graphical input data to a format compatible with said pipeline of said graphics processing unit;

after said converting, a cache distributor receiving said graphical input data from said front end, said cache distributor is coupled to said front end;

virtually addressing each of said enabled processing elements above a translator to virtually process said graphical input data;

said translator receiving said graphical input data from said cache distributor;

said translator mapping virtual addresses of each of said enabled processing elements to physical addresses of said enabled processing elements in said plurality of processing elements, said mapping comprises using a mapping table, said translator is coupled to said cache distributor;

physically processing said graphical input data at said physical addresses of said enabled processing elements, said plurality of processing elements are coupled to said translator; and

physically addressing each of said enabled processing elements below said translator to further process said graphical input data.

20. The computer system of claim 19, said method further comprising:

before said receiving said graphical input data, disabling a first processing element by setting a validity fuse corresponding to said first processing element; and

wherein said determining a number of enabled processing elements comprises checking status of a corresponding validity fuse for each of said plurality of processing elements, wherein a set fuse indicates a processing element that is disabled, and an intact fuse indicates an enabled processing element.

21. The computer system of claim 20, wherein said setting said validity fuse comprises breaking a physical, electrical fuse connection.

22. The computer system of claim 19, said method further comprising:

before said receiving said graphical input data, disabling a first processing element through a software override; and

wherein said determining a number of enabled processing elements comprises recognizing said software override that indicates said first processing element is disabled.

23. The computer system of claim 22, said method further comprising:

reenabling said first processing element by disengaging said software override.

24. The computer system of claim 19, wherein said mapping virtual addresses comprises:

mapping virtual representations of cache entries in a cache memory corresponding to said enabled processing elements that are virtualized to physical representations of said cache entries in said cache memory corresponding to said processing elements.

25. The computer system of claim 24, wherein said mapping is a one-to-one relationship between virtual representations and physical representations of cache entries in said cache memory.

26. The computer system of claim 24, wherein said mapping virtual addresses further comprises:

load balancing said virtual representations of cache entries between cache entries corresponding to said enabled processing elements.

27. The computer system of claim 26, wherein said load balancing comprises:

load balancing said virtual representations of cache entries by assigning consecutive cache entries to one of said enabled processing elements.

28. The computer system of claim 19, wherein said plurality of processing elements comprises a plurality of vertex processing engines (VPE), and said pipeline comprises a vertex pipeline.

29. The computer system of claim 19, wherein said translator comprises a vertex attribute buffer (VAB).