System and method for high speed packet transmission

• US 8,718,051 B2
• Filed: 10/29/2009
• Issued: 05/06/2014
• Est. Priority Date: 05/15/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai
• Primary Examiner(s): Pham, Brenda H
• Application Number:
  US12/608,985
• Publication Number:
  US 20100046521A1
• Time in Patent Office: 1,650 Days
• Field of Search: 370/389, 370/359, 370/396, 370/395.71, 370/1, 370/402, 370/428
• US Class Current: 370/359
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04Q 11/0428 Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Abstract

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Claims

1. A system comprising:

a blade, the blade comprising;

one or more ports for receiving or transmitting packets; and

an integrated circuit, the integrated circuit comprising;

a first core; and

a second core;

wherein the first core comprises a first switching circuit operative to transfer a first packet from the second core to the first core; and

wherein the second core comprises a second switching circuit operative to transfer a second packet from the first core to the second core.

2. The system of claim 1 wherein the first core is operative to store the first packet in the second switching circuit and the second core is operative to retrieve the first packet from the second switching circuit.

3. The system of claim 1 wherein:

the first core is operative to store the first packet in the second switching circuit and the second core is operative to retrieve the first packet from the second switching circuit; and

the second core is operative to store the second packet in the first switching circuit and the first core is operative to retrieve the second packet from the first switching circuit.

4. The system of claim 1 wherein the first switching circuit is a FIFO.

5. The system of claim 1 wherein the second switching circuit is a FIFO.

6. The system of claim 1 wherein the first core further comprises a first processor that determines whether to transfer the first packet to the second core.

7. The system of claim 6 wherein the first processor determines whether to transfer the first packet from the first core to the second core by analyzing a portion of the first packet.

8. The system of claim 6 wherein the first processor determines whether to transfer the first packet from the first core to the second core by extracting a forward identifier from the first packet and analyzing the forward identifier.

9. The system of claim 6 wherein the second core further comprises a second processor that determines whether to transfer the second packet to the first core.

10. The system of claim 1 wherein the first packet is the same as the second packet.

11. The system of claim 1 further comprising:

another blade; and

a backplane coupled to the blades for transmission of packets between the blades;

wherein transfer of a packet between the first core and the second core does not comprise transmitting the packet over the backplane.

12. A system comprising:

a blade, the blade comprising;

one or more ports for receiving or transmitting packets; and

an integrated circuit, the integrated circuit comprising;

a first core; and

a second core;

wherein the first core comprises a first switching circuit operative to transfer a first packet from the first core to the second core; and

wherein the second core comprises a second switching circuit operative to transfer a second packet from the second core to the first core.

13. The system of claim 12 wherein the first core is operative to store the first packet in the first switching circuit and the second core is operative to retrieve the first packet from the first switching circuit.

14. The system of claim 12 wherein:

the first core is operative to store the first packet in the first switching circuit and the second core is operative to retrieve the first packet from the first switching circuit; and

the second core is operative to store the second packet in the second switching circuit and the first core is operative to retrieve the second packet from the second switching circuit.

15. The system of claim 12 wherein the first switching circuit is a FIFO.

16. The system of claim 12 wherein the second switching circuit is a FIFO.

17. The system of claim 12 wherein the first core further comprises a first processor that determines whether to transfer the first packet to the second core.

18. The system of claim 17 wherein the first processor determines whether to transfer the first packet from the first core to the second core by analyzing a portion of the first packet.

19. The system of claim 17 wherein the first processor determines whether to transfer the first packet from the first core to the second core by extracting a forward identifier from the first packet and analyzing the forward identifier.

20. The system of claim 17 wherein the second core further comprises a second processor that determines whether to transfer the second packet to the first core.

21. The system of claim 12 wherein the first packet is the same as the second packet.

22. The system of claim 12 further comprising:

another blade; and

a backplane coupled to the blades for transmission of packets between the blades;

wherein transfer of a packet between the first core and the second core does not comprise transmitting the packet over the backplane.

23. A method comprising:

receiving a packet at a first core of an integrated circuit of a blade, the blade comprising the integrated circuit and one or more ports for receiving or transmitting packets, the integrated circuit comprising the first core and a second core;

analyzing the packet at the first core to determine whether to transfer the packet to the second core of the integrated circuit; and

upon determining to transfer the packet to the second core, storing the packet in a switching circuit located in the second core.

24. The method of claim 23 further comprising retrieving the packet from the switching circuit.

25. The method of claim 23 wherein analyzing the packet further comprises extracting a forward identifier from the packet.

26. The method of claim 24 wherein retrieving the packet does not comprise transmitting the packet over a backplane coupled to blades.

27. A method comprising:

receiving a packet at a first core of an integrated circuit of a blade, the blade comprising the integrated circuit and one or more ports for receiving or transmitting packets, the integrated circuit comprising the first core and a second core;

analyzing the packet at the first core to determine whether to transfer the packet to the second core of the integrated circuit;

upon determining to transfer the packet to the second core, storing the packet in a switching circuit located in the first core

polling the switching circuit in the first core to determine if the switching circuit has packets to be retrieved by the second core.

28. The method of claim 27 further comprising retrieving the packet from the switching circuit upon determining that the switching circuit has packets designated for the second core.

29. The method of claim 27 wherein analyzing the packet further comprises extracting a forward identifier from the packet.

30. The method of claim 28 wherein retrieving the packet does not comprise transmitting the packet over a backplane coupled to blades.