Low output skew double data rate serial encoder
First Claim
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1. A serial encoder, comprising:
- a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output;
a plurality of data input flip-flops coupled to the data inputs of the multiplexer;
a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and
a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage, and the final data register stage is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder, and wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer.
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Abstract
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.
385 Citations
42 Claims
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1. A serial encoder, comprising:
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a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; a plurality of data input flip-flops coupled to the data inputs of the multiplexer; a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage, and the final data register stage is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder, and wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A serial encoder, comprising:
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means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, wherein said register stage is separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A serial encoder, comprising:
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a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; a plurality of data input flip-flops coupled to the data inputs of the multiplexer; a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage and wherein the output of the serial encoder is solely determined by two signals from the final data register stage of the synchronizing circuit, thereby resulting in a low output skew of the encoder, wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer. - View Dependent Claims (18, 19, 20, 21)
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22. A serial encoder, comprising:
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means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, and wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder. - View Dependent Claims (23, 24, 25)
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26. A storage media comprising program instructions which are computer-executable to serially encode data by employing:
a serial encoder, comprising; a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; a plurality of data input flip-flops coupled to the data inputs of the multiplexer; a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage; and
the final data register stage is separated by a single logic layer from the output of the serial encoder,the storage media comprising; (a) program instructions that cause a low output skew of the encoder; and
,(b) program instructions that cause output glitches from the output of the multiplexer to be substantially eliminated. - View Dependent Claims (27, 28, 29)
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30. A storage media comprising program instructions which are computer-executable to serially encode data by employing:
a serial encoder, comprising; a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; a plurality of data input flip-flops coupled to the data inputs of the multiplexer; a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing, circuit comprises a final data register stage, the storage media comprising; program instructions that cause the output of the serial encoder to be determined solely based on two signals from the final data register stage;
of the synchronizing circuit, thereby resulting in a low output skew of the encoder; andprogram instructions that cause output glitches from the output of the multiplexer to be substantially eliminated. - View Dependent Claims (31, 32)
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33. A method of serial encoding, comprising:
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providing a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; providing a plurality of data input flip-flops coupled to the data inputs of the multiplexer; providing a plurality of select input flip-flops coupled to the select inputs of the multiplexer; providing a synchronizing circuit coupled to the output of the multiplexer and providing an output of a serial encoder, wherein the synchronizing circuit comprises a final data register stage, and the final data register stage is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder; and employing the synchronizing circuit to substantially eliminate output glitches from the output of the multiplexer. - View Dependent Claims (34, 35, 36, 37, 38)
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39. A method of serial encoding, comprising:
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providing a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; providing a plurality of data input flip-flops coupled to the data inputs of the multiplexer; providing a plurality of select input flip-flops coupled to the select inputs of the multiplexer; providing a synchronizing circuit coupled to the output of the multiplexer and providing an output of a serial encoder, wherein the synchronizing circuit comprises a final data register stage and wherein the output of the serial encoder is solely determined by two signals from the final data register stage of the synchronizing circuit, thereby resulting in a low output skew of the encoder; and employing the synchronizing circuit to substantially eliminates output glitches from the output of the multiplexer. - View Dependent Claims (40, 41, 42)
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Specification