Apparatus and method for processing a wirelessly received information encoded in form of embedded data and clock

• US 8,738,957 B2
• Filed: 02/02/2012
• Issued: 05/27/2014
• Est. Priority Date: 06/06/2008
• Status: Active Grant

• Current Assignee: Roche Diabetes Care Inc. (Roche Holding AG)
• Original Assignee: Roche Diagnostics Operations Incorporated (Roche Holding AG)
• Inventors: Fehr, Jean-Noel, Von Buren, Thomas, Anliker, Urs
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Chen, Xuxing
• Application Number:
  US13/364,546
• Publication Number:
  US 20120166858A1
• Time in Patent Office: 845 Days
• Field of Search: 713/500
• US Class Current: 713/500
• CPC Class Codes: G16H 40/20 for the management or administration of healthcare resources or facilities, e.g. managing hospital staff or surgery rooms
• CPC Class Codes: G16H 40/67 for remote operation
• CPC Class Codes: H04B 1/7156 Arrangements for sequence synchronisation

Abstract

An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14) may include a first processor (18) that controls only wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12), a second processor (16) that controls the operations associated only with the electronic device (12) and excluding the wireless communications with the another device (14), and means (30-30″″) for extracting the clock information and the data from the wirelessly received information and providing a corresponding clock signal and the data to the second processor (16) for synchronous receipt of the data by the second processor (16) using the clock signal.

Claims

1. An electronic device for processing information wirelessly received from another electronic device, the wirelessly received information including embedded data and clock information, the electronic device comprising:

a first processor configured to extract at least one information packet containing the embedded data and clock information from the information wirelessly received by the electronic device from the another electronic device and to produce the at least one information packet at an output thereof,

a clock and data decoding circuit having an input connected to the output of the first processor and an output, the clock and decoding circuit configured to extract the clock information from the at least one information packet, to fully decode the data from the at least one information packet, and to produce the fully decoded data and a clock signal corresponding to the extracted clock information at the output thereof, and

a second processor having an input connected to the output of the clock and data decoding circuit, the second processor configured to synchronously read the fully decoded data received from the clock and data decoding circuit using the clock signal received from the clock and data decoding circuit, and to thereafter process the fully decoded data.

2. The electronic device of claim 1 wherein the output of the clock and data decoding circuit comprises a first output connected to the input of the second processor and a second output, separate from the first output, connected to the input of the second processor, and wherein the clock and data decoding circuit comprises:

a phase lock loop circuit having an input coupled to the output of the first processor, a first output defining the first output of the clock and data decoding circuit and a second output, the phase lock loop circuit configured to extract the clock information from the at least one information packet and produce the clock signal at the first output thereof, and

a decoder circuit having a first input connected to the output of the first processor, a second input connected to the second output of the phase lock loop circuit and an output defining the second output of the clock and data decoding circuit, the decoder circuit configured to fully decode the data from the at least one information packet and produce the fully decoded data at the output thereof.

3. The electronic device of claim 2 wherein the phase lock loop circuit is configured to produce a phase lock loop clock signal at the second output thereof,

and wherein the decoder circuit is configured to fully decode the data in the at least one information packet using the phase lock loop clock signal.

4. The electronic device of claim 3 wherein the information wirelessly received by the electronic device from the another electronic device further comprises a preamble that precedes the at least one information packet,

and wherein the first processor is configured to extract the preamble from the information wirelessly received by the electronic device from the another electronic device and to produce the extracted preamble at the output thereof,

and wherein the phase lock loop circuit is configured to be responsive to the preamble to lock and run at a phase lock loop clock rate determined by information in the preamble, and to produce the phase lock loop clock signal at the phase lock loop clock rate.

5. The electronic device of claim 4 wherein the decoder circuit is configured to fully decode the data in the at least one information packet by removing the clock information from the at least one information packet as a function of the phase lock loop clock signal.

6. The electronic device of claim 4 wherein the phase lock loop circuit is configured to be responsive to transitions in values of the data contained in the at least one information packet to update the phase lock loop clock rate.

7. The electronic device of claim 1 wherein the information wirelessly received by the first processor from the another electronic device is received by the first processor in two separate channels in which a first channel contains the data and a second channel contains the clock information,

and wherein the clock and data decoding circuit comprises means for processing the first channel to fully decode the data and means for processing the second channel to extract the clock signal from the clock information.

8. The electronic device of claim 7 in which the first channel is a data channel and in which the second channel is an audio channel.

9. The electronic device of claim 1 wherein the first processor is configured to wirelessly receive information from the another electronic device according to a predefined communication protocol,

and wherein the first processor is configured to extract the at least one information packet from the information wirelessly received by the electronic device from the another electronic device according to the predefined communication protocol.

10. The electronic device of claim 1 wherein the information wirelessly received by the electronic device from the another electronic device is received as a wireless signal comprising self clocking codes in which the data and the clock information are combined into the wireless signal.

11. The electronic device of claim 3 wherein the information wirelessly received by the electronic device from the another electronic device further comprises a preamble that precedes the at least one information packet,

and wherein the first processor is configured to extract the preamble from the information wirelessly received by the electronic device from the another electronic device and to produce the extracted preamble at the output thereof,

and wherein the phase lock loop circuit is normally in a sleep state and is configured to be responsive to the preamble to wake up from the sleep state and to lock and run with a phase lock loop clock that operates at a phase lock loop clock rate defined by information contained in the preamble.