Solid-state imaging element having image signal overflow path

• US 8,743,257 B2
• Filed: 05/10/2011
• Issued: 06/03/2014
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ueno, Takahisa, Yonemoto, Kazuya, Suzuki, Ryoji, Shiono, Koichi
• Primary Examiner(s): WHIPKEY, JASON T
• Application Number:
  US13/067,112
• Publication Number:
  US 20110211101A1
• Time in Patent Office: 1,120 Days
• Field of Search: 348/308, 257/292, 257/225, 257/226, 257/227, 257/228, 257/229, 257/230, 257/231, 257/232, 257/233, 257/234, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/441 by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Since the great number of elements constituting a unit pixel having an amplification function would hinder reduction of pixel size, unit pixel n,m arranged in a matrix form is comprised of a photodiode, a transfer switch for transferring charges stored in the photodiode, a floating diffusion for storing charges transferred by the transfer switch, a reset switch for resetting the floating diffusion, and an amplifying transistor for outputting a signal in accordance with the potential of the floating diffusion to a vertical signal line, and by affording vertical selection pulse φVn to the drain of the reset switch to control a reset potential thereof, pixels are selected in units of rows.

Claims

1. A solid-state imaging element comprising:

a separating portion between a photoelectric conversion element and an area, said area being configured to receive a pixel source voltage;

a transfer switch between said photoelectric conversion element and a floating diffusion, said floating diffusion being between said transfer switch and a reset switch; and

a path at said separating portion, said path being configured to discharge a charge,

wherein an output circuit outputs signals read into vertical signal lines in voltage mode,

wherein said floating diffusion is connected to a gate of an amplifying transistor.

2. A solid-state imaging element comprising:

a photoelectric conversion element of a first conductivity type at a surface of a substrate, said photoelectric conversion element being configured to convert incident light into a signal charge;

an overflow path of a second conductivity type within said substrate, said second conductivity type being opposite to said first conductivity type;

an area of the first conductivity type at said surface of the substrate, said overflow path being between said photoelectric conversion element and said area;

a floating diffusion of the first conductivity type at said surface of the substrate, a channel region of a transfer switch being between said photoelectric conversion element and said floating diffusion.

3. A solid-state imaging element as claimed in claim 2, wherein said overflow path is configured to transfer an amount of the signal charge to said area.

4. A solid-state imaging element as claimed in claim 2, wherein said first conductivity type is N-type and said second conductivity type is P-type.

5. A solid-state imaging element as claimed in claim 2, wherein said overflow path touches said photoelectric conversion element and said area.

6. A solid-state imaging element as claimed in claim 2, wherein said area is electrically connected to a pixel source line.

7. A solid-state imaging element as claimed in claim 2, wherein a quantity of the signal charge is in accordance with a quantity of the incident light.

8. A solid-state imaging element as claimed in claim 2, further comprising:

a gate electrode of the transfer switch electrically connected to a transfer line, said surface of the substrate being between said channel region of the transfer switch and said gate electrode of the transfer switch.

9. A solid-state imaging element as claimed in claim 2, further comprising:

a gate electrode of an amplifying transistor electrically connected to said floating diffusion, said surface of the substrate being between a channel region of the amplifying transistor and said gate electrode of the amplifying transistor.

10. A solid-state imaging element as claimed in claim 9, further comprising:

a drain electrode of the amplifying transistor at said surface of the substrate, said channel region of the amplifying transistor being between said source electrode of the amplifying transistor and said drain electrode of the amplifying transistor.

11. A solid-state imaging element as claimed in claim 9, further comprising:

a different overflow path of the second conductivity type within said substrate, said different overflow path being between a drain of a reset switch and a source of the amplifying transistor.

12. A solid-state imaging element as claimed in claim 11, wherein said source of the amplifying transistor is of said first conductivity type.

13. A solid-state imaging element as claimed in claim 11, wherein said drain of the reset switch is of said first conductivity type.

14. A solid-state imaging element as claimed in claim 11, wherein said different overflow path touches said drain of the reset switch and said source of the amplifying transistor.

15. A solid-state imaging element as claimed in claim 11, further comprising:

a channel region of the reset switch between said floating diffusion and said drain of the reset switch.

16. A solid-state imaging element as claimed in claim 15, further comprising:

a gate electrode of the reset switch electrically connected to a reset line, said surface of the substrate being between said channel region of the reset switch and said gate electrode of the reset switch.

17. A solid-state imaging element as claimed in claim 11, further comprising:

an oxide touching the different overflow path, said oxide touching the different overflow path being at said surface of the substrate.

18. A solid-state imaging element as claimed in claim 17, wherein said oxide touching the different overflow path is a LOCOS oxide.

19. A solid-state imaging element as claimed in claim 2, further comprising:

an oxide touching the overflow path, said oxide touching the overflow path being at said surface of the substrate.

20. A solid-state imaging element as claimed in claim 19, wherein said oxide touching the overflow path is a LOCOS oxide.