Multi-stack semiconductor integrated circuit device

• US 8,744,349 B2
• Filed: 10/08/2010
• Issued: 06/03/2014
• Est. Priority Date: 10/15/2009
• Status: Active Grant

• Current Assignee: ThruChip Japan Inc.
• Original Assignee: KEIO University
• Inventors: Kuroda, Tadahiro
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US13/501,879
• Publication Number:
  US 20120217658A1
• Time in Patent Office: 1,334 Days
• Field of Search: 455/41.1, 455/41.2, 455/66.1, 257/686
• US Class Current: 455/41.1
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H04B 5/26 : using coils
• CPC Class Codes: H04B 5/72 : for local intradevice communication

Abstract

The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception.

Claims

1. A multi-stack semiconductor integrated circuit device having a stack structure comprising:

four or more semiconductor chips having the same shape and being stacked on top of each other, wherein each semiconductor chip comprises;

a first coil for transmission/reception for communication between chips over a long distance; and

a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of said first coil for transmission/reception

wherein a semiconductor chip, of which the size is smaller than that of said semiconductor chips and which has a different shape and only a third coil for transmission/reception for communication between chips having the same size as that of said second coil for transmission/reception, is stacked on the top or bottom semiconductor chip in said stack structure.

2. The multi-stack semiconductor integrated circuit device according to claim 1, wherein

said first coil for transmission/reception and said second coil for transmission/reception are polygonal, and

the diameter of the circle that inscribes said first coil for transmission/reception and said second coil for transmission/reception is 1 to 3 times greater than the distance for communication between chips that has been set in accordance with the size of the coils.

3. The multi-stack semiconductor integrated circuit device according to claim 2, wherein the diameter of the circle that inscribes said first coil for transmission/reception is 4 to 36 times greater than the pitch at which said semiconductor chips are stacked on top of each other.

4. The multi-stack semiconductor integrated circuit device according to claim 1, wherein said multi-stack structure comprises at least:

a first semiconductor chip group where a predetermined number of semiconductor chips are stacked on top of each other in such a manner that a first pair of sides of each semiconductor chip is aligned with that of the semiconductor chip at the bottom, and a second pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a first direction in which said first pair of sides runs;

a second semiconductor chip group where a predetermined number of semiconductor chips are stacked on top of each other in such a manner that a second pair of sides of each semiconductor chip is aligned with the second pair of the semiconductor chip at the top of said first semiconductor chip group, and a first pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a second direction in which said second pair of sides runs;

a third semiconductor chip group where the same number of semiconductor chips as in the first semiconductor chip group are stacked on top of each other in such a manner that a first pair of sides of each semiconductor chip is aligned with the first pair of sides of the semiconductor chip at the top of said second semiconductor chip group, and a second pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a third direction that is opposite to said first direction; and

a fourth semiconductor chip group where the same number of semiconductor chips as in said second semiconductor chip group are stacked on top of each other in such a manner that a second pair of sides of each semiconductor chip is aligned with the second pair of the semiconductor chip at the top of said third semiconductor chip group, and a first pair of sides of each semiconductor chip is shifted by a predetermined pitch sequentially in a fourth direction that is opposite to said second direction.

5. The multi-stack semiconductor integrated circuit device according to claim 1, wherein said semiconductor chips having the same shape are flash memory chips and said semiconductor chip having a different shape is a controller chip for controlling the operation of said flash memories.