High data rate transmitter and receiver

• US 8,744,389 B2
• Filed: 10/12/2011
• Issued: 06/03/2014
• Est. Priority Date: 12/06/2001
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Holding 73 LLC (Intellectual Ventures LLC)
• Inventors: Lakkis, Ismail, Bahreini, Yasaman, Santhoff, John
• Primary Examiner(s): Trinh, Sonny
• Application Number:
  US13/317,224
• Publication Number:
  US 20120033714A1
• Time in Patent Office: 965 Days
• Field of Search: 455/161.1, 455/165.1, 455/313, 455/323, 370/310
• US Class Current: 455/190.1
• CPC Class Codes: H04B 1/71632 Signal aspects H04B1/7172 and H04B1/7176 take precedence
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence

Abstract

A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Claims

1. A receiver comprising:

a front end configured to receive a communication signal that has a fractional bandwidth in a range between approximately 20 percent and approximately 200 percent;

an analog to digital converter configured to directly convert the radio frequency signal into a data signal;

a processing device configured to receive the data signal and to produce a plurality of data frames, determine a de-spreading code, and de-spread the data signal using the de-spreading code, wherein the de-spreading code is selected from a group consisting of;

a 1-bit code, a 2-bit code, a 4-bit code, an 8-bit code, a 16-bit code, a 32-bit code, a 64-bit code, a 128-bit code, and a 256-bit code; and

a medium access controller configured to receive the plurality of data frames and convert the data frames to data.

2. The receiver of claim 1, wherein the processing device is a digital baseband processor.

3. The receiver of claim 1, wherein the communication signal is an ultra-wideband signal.

4. The receiver of claim 1, wherein a center frequency of the communication signal is between 3.0 Giga-Hertz and 11.0 Giga-Hertz.

5. The receiver of claim 1, wherein the analog to digital converter is selected from a group consisting of:

a 1-bit converter, a 2-bit converter, a 4-bit converter, a 6-bit converter, and an 8-bit converter.

6. The receiver of claim 1, wherein the processing device includes a poly-phase filter.

7. The receiver of claim 6, wherein the poly-phase filter comprises a decimator configured to decimate the data signal.

8. The receiver of claim 1, wherein the processing device is configured to descramble the data signal.

9. The receiver of claim 1, wherein the processing device is configured to de-interleave the data signal.

10. The receiver of claim 1, wherein the processing device comprises a forward error detection decoding algorithm.

11. The receiver of claim 10, wherein the forward error detection decoding algorithm is a low density parity check algorithm.

12. The receiver of claim 1, wherein the data frames comprise a physical layer header, a medium access control header, a rate field and a plurality of data packets.

13. The receiver of claim 12, wherein the physical layer header, the medium access control header, and the plurality of data packets have different spreading codes.

14. The receiver of claim 1, wherein the communication signal is transmitted through a wire media from a transmitter, and wherein the wire media is selected from a group consisting of:

a an optical fiber ribbon, a fiber optic cable, a single mode fiber optic cable, a multi-mode fiber optic cable, a twisted pair wire, an unshielded twisted pair wire, a plenum wire, a PVC wire, and a coaxial cable.

15. The receiver of claim 1, wherein the front end comprises at least two receive antennas.

16. The receiver of claim 15, wherein the at least two receive antennas are separated by a distance of greater than one wavelength of a center frequency of the communication signal.

17. The receiver of claim 1, wherein the processing device is further configured to:

measure communication channel impulse responses of the data signal with at least one code at a plurality of time periods;

determine a signal strength and a starting time for multipath signals based upon the communication channel impulse responses; and

sum energy of the multipath signals to create the data signal.

18. A method comprising:

receiving a communication signal that has a fractional bandwidth in a range between approximately 20 percent and approximately 200 percent;

directly converting, using an analog to digital converter, the radio frequency signal into a data signal;

determining, using a processor, a de-spreading code;

de-spreading, using the processor, the data signal using the de-spreading code, and wherein the de-spreading code is selected from a group consisting of;

a 1-bit code, a 2-bit code, a 4-bit code, an 8-bit code, a 16-bit code, a 32-bit code, a 64-bit code, a 128-bit code, and a 256-bit code;

producing, using the processor, a plurality of data frames from the de-spread data signal;

receiving, using a medium access controller, the plurality of data frames; and

converting, using the medium access controller, the data frames to data.

19. The method of claim 18, wherein the processor is a digital baseband processor.

20. The method of claim 18, further comprising:

measuring communication channel impulse responses of the data signal with at least one code at a plurality of time periods;

determining a signal strength and a starting time for multipath signals based upon the communication channel impulse responses; and

summing energy of the multipath signals to create the data signal.