Method of fabricating semiconductor device

• US 8,748,266 B2
• Filed: 11/08/2011
• Issued: 06/10/2014
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Numazawa, Sumito, Nakazawa, Yoshito, Kobayashi, Masayoshi, Kudo, Satoshi, Imai, Yasuo, Kubo, Sakae, Shigematsu, Takashi, Ohnishi, Akihiro, Uesawa, Kozo, Oishi, Kentaro
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US13/291,999
• Publication Number:
  US 20120052675A1
• Time in Patent Office: 945 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A manufacturing method of a semiconductor device including a metal-insulator-semiconductor-field-effect transistor (MISFET), comprising steps of:

(a) forming a trench in a semiconductor substrate;

(b) after the step (a), forming a first insulating film over a bottom surface of the trench, over a side surface of the trench and over an edge portion of the trench by a thermal oxidation method, the edge portion being an intersection between the side surface of the trench and a surface of the semiconductor substrate;

(c) after the step (b), forming a second insulating film over the first insulating film by a chemical vapor deposition (CVD) method, and

(d) after the step (c), forming a first conductive film over the second insulating film, thereby the trench is filled with the first conductive film, the second insulating film and the first insulating film;

wherein the first and second insulating films constitute a gate insulating film of the MISFET,

wherein the first conductive film constitutes a gate electrode of the MISFET,

wherein the edge portion of the trench has a sloping shape from the surface of the semiconductor substrate to the side surface of the trench,

wherein, after said step (d), said first and second insulating films are kept on the bottom surface of the trench, on the side surface of the trench, and on the sloping shape of the edge portion of the trench,

wherein, after the step (d), a thickness of the second insulating film formed over the side surface of the trench and over the edge portion of the trench having the sloping shape is greater than a thickness of the first insulating film formed over the side surface of the trench, and

wherein the second insulating film consists essentially of silicon oxide and directly contacts the first insulating film.

2. The manufacturing method of the semiconductor device according to the claim 1, further comprising a step of:

(e), between said steps (a) and (b), performing a dry etching to the trench such that the edge portion of the trench and the bottom of the trench become smooth, thereby the sloping shape is formed in the edge portion of the trench.

3. The manufacturing method of the semiconductor device according to the claim 1, further comprising the steps of:

(f), after the step (a), forming a third insulating film over the bottom surface of the trench and over the side surface of the trench by a thermal oxidation method, and

(g) after the steps (f) and before the step (b), removing the third insulating film.

4. The manufacturing method of the semiconductor device according to the claim 1,

wherein, after the step (d), a thickness of the second insulating film formed over the bottom surface of the trench is greater than a thickness of the first insulating film formed over the bottom surface of the trench.

5. The manufacturing method of the semiconductor device according to the claim 1,

wherein the first insulating film is formed of a silicon oxide film.