Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor

• US 8,749,561 B1
• Filed: 03/14/2003
• Issued: 06/10/2014
• Est. Priority Date: 03/14/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Diercks, Dwight D., de Waal, Abraham B.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US10/390,120
• Time in Patent Office: 4,106 Days
• Field of Search: 345/502, 345/542, 345/505, 345/501, 345/530, 345/531, 345/536, 345/503
• US Class Current: 345/503
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Claims

1. A system for coordinated data execution in a computer system, comprising:

a primary graphics processor coupled to a local graphics memory;

an integrated graphics processor coupled to a system memory;

a graphics bus coupling the primary graphics processor and the integrated graphics processor, wherein the primary graphics processor and the integrated graphics processor are configured for coordinated data execution via communication across the graphics bus and for selectively allocating a first portion of graphics processing operations to the primary graphics processor and a second portion of graphics processing operations to the secondary graphics processor for execution to render a 3-D display, and wherein the integrated graphics processor is allocated transform and lighting operations, and wherein the secondary graphics processor utilizes a high communications bandwidth with system memory to implement texture map reordering, texture compression, decryption and decoding of video.

2. The system of claim 1 wherein the integrated graphics processor is integrated into a North bridge of the computer system.

3. The system of claim 2 wherein the integrated graphics processor is configured to use a portion of system memory for dedicated local memory.

4. The system of claim 2 wherein the primary graphics processor is detachably coupled to the graphics bus by a connector.

5. The system of claim 2 wherein the primary graphics processor is configured to communicate with the local graphics memory via a high speed local bus and the integrated graphics processor is configured to communicate with the system memory via a high speed system memory bus, wherein the primary graphics processor communicates with the integrated graphics processor via a low speed graphics bus.

6. The system of claim 2 wherein the integrated graphics processor is configured to perform graphics processing operations that occur in a first portion of a graphics rendering pipeline.

7. The system of claim 2 wherein the primary graphics processor is configured to perform graphics processing operations that occur in a second portion of a graphics rendering pipeline.

8. The system of claim 2 wherein the primary graphics processor is configured to process commands from a thread that is different from a thread being processed by the integrated graphics processor.

9. The system of claim 1 wherein the integrated graphics processor comprises at least one shader unit.

10. A dual GPU (graphics processor unit) system for coordinated graphics data execution, comprising:

a first GPU capable of performing independent graphics processing coupled to a local graphics memory;

a second GPU capable of performing independent graphics processing coupled to a system memory, the second GPU integrated with a memory controller;

a graphics bus coupling the first GPU and the second GPU, wherein the first GPU and the second GPU are configured for coordinated parallel data execution via communication across the graphics bus, and wherein the coordinated parallel data execution is selectively allocating a first portion of graphics operations to the first GPU and a second portion of graphics operations to the second GPU to render a 3-D display, wherein the second GPU is allocated transform and lighting operations, and wherein the secondary graphics processor utilizes a high communications bandwidth with system memory to implement texture map reordering, texture compression, decryption and decoding of video.

11. The system of claim 10 wherein the second GPU is integrated with a North bridge of the computer system.

12. The system of claim 11 wherein the North bridge is coupled to the system memory via a system bus and the North bridge is coupled to a CPU via a front-side bus.

13. The system of claim 10 wherein the first GPU is a graphics card mounted GPU and the graphics card is detachably coupled to the graphics bus by a connector.

14. The system of claim 10 wherein the graphics bus is in accordance with a version of an AGP standard.

15. The system of claim 10 wherein the first GPU includes a plurality of shader units and is configured to perform graphics processing operations that occur in a second portion of a graphics rendering pipeline.

16. The system of claim 15 wherein the graphics operations that occur in the second portion of the graphics pipeline includes anti-aliasing, bump mapping, or texture mapping.

17. The system of claim 10 wherein the second GPU is configured to perform graphics processing operations that occur in a first portion of a graphics rendering pipeline.

18. The system of claim 17 wherein the graphics operations that occur in the first portion of the pipeline includes back face culling, occlusion culling, view frustrum culling, transform, or lighting.

19. The system of claim 10 wherein the second GPU is configured to perform pre-processing operations in conjunction with a CPU.

20. The system of claim 19 wherein the pre-processing operations includes texture map reordering, texture compression, or video decoding.

21. A method for coordinated data execution using a primary graphics processor and a secondary graphics processor, comprising:

executing a graphics application;

executing a graphics driver for interfacing with the graphics application;

dividing graphics operations from the application into a first set of operations and a second set of operations;

processing the first set of operations using a primary graphics processor; and

processing the second set of operations using a secondary graphics processor, wherein the secondary graphics processor is integrated with a North bridge of the computer system, and wherein the primary graphics processor and the secondary graphics processor are coupled via a graphics bus for coordinated data execution by the primary graphics processor and the secondary graphics processor executing graphics commands cooperatively and in parallel to render a 3-D display, and wherein the secondary graphics processor is allocated transform and lighting graphics processing, and wherein the secondary graphics processor utilizes a high communications bandwidth with system memory to implement texture map reordering, texture compression, decryption and decoding of video.

22. The method of claim 21 wherein the primary graphics processor is coupled to a local graphics memory and the secondary graphics processor is configured to use a portion of a system memory for a dedicated local graphics memory.

23. The method of claim 22 wherein the secondary graphics processor communicates with a CPU of the computer system via a front side bus.

24. The method of claim 22 wherein the primary graphics processor is detachably coupled to the graphics bus by a connector.

25. The method of claim 22 further comprising:

performing graphics processing operations that occur in a first portion of a graphics rendering pipeline by using the secondary graphics processor, wherein the graphics operations that occur in the first portion of the pipeline includes back face culling, occlusion culling, view frustrum culling, transform, or lighting.

26. The method of claim 22 further comprising:

performing graphics processing operations that occur in a second portion of a graphics rendering pipeline by using the primary graphics processor, wherein the graphics operations that occur in the second portion of the graphics pipeline includes anti-aliasing, bump mapping, or texture mapping.

27. The method of claim 21 wherein the primary graphics processor is configured to process commands from a thread that is different from a thread being processed by the secondary graphics processor.

28. A non-transitory computer readable information store for implementing a method for coordinated data execution using a primary graphics processor and a secondary graphics processor, the information store having computer readable code which when executed by a computer system cause the computer system to implement a method comprising:

executing a graphics application;

executing a graphics driver for interfacing with the graphics application;

dividing graphics operations from the application into a first set of operations and a second set of operations as determined by the graphics driver;

processing the first set of operations using a primary graphics processor; and

processing the second set of operations using a secondary graphics processor, wherein the secondary graphics processor is integrated into a North bridge of the computer system, and wherein the primary graphics processor and the secondary graphics processor are coupled via a graphics bus for coordinated graphics processing execution by the primary graphics processor and the secondary graphics processor executing graphics commands cooperatively and in parallel to render a 3-D display, and wherein the primary graphics processor and the secondary graphics processor are each capable of performing independent graphics processing, and wherein the primary graphics processor performs graphics processing operations that occur in a second portion of a graphics rendering pipeline and the secondary graphics processor performs graphics processing operations that occur in a first portion of the graphics rendering pipeline, said first portion including transform and lighting operations, and wherein the secondary graphics processor utilizes a high communications bandwidth with system memory to implement texture map reordering, texture compression, decryption and decoding of video.

29. The non-transitory computer readable information store of claim 28 wherein the primary graphics processor is coupled to a local graphics memory and the secondary graphics processor is configured to use a portion of a system memory as a dedicated local graphics memory.

30. The non-transitory computer readable information store of claim 29 wherein the graphics bus is an AGP graphics bus.

31. The non-transitory computer readable information store of claim 29 wherein the primary graphics processor is detachably coupled to the graphics bus by a connector.

32. The non-transitory computer readable information store of claim 28 wherein the graphics processing operations that occur in the first portion of the pipeline includes back face culling, occlusion culling, view frustrum culling, transform, or lighting.

33. The non-transitory computer readable information store of claim 28 wherein the graphics processing operations that occur in the second portion of the graphics pipeline includes anti-aliasing, bump mapping, or texture mapping.

34. The non-transitory computer readable information store of claim 28 wherein the primary graphics processor is configured to process commands from a thread that is different from a thread being processed by the secondary graphics processor.