Semiconductor device

• US 8,759,946 B2
• Filed: 11/13/2007
• Issued: 06/24/2014
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tokunaga, Hajime
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US11/979,992
• Publication Number:
  US 20080116500A1
• Time in Patent Office: 2,415 Days
• Field of Search: 257/50, 257/530, 257/E23.147, 438/131, 438/467, 438/600, 365/96
• US Class Current: 257/530
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02496 Layer structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/0256 Selenides
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 21/02683 Continuous wave laser beam
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A semiconductor device which does not reduce writing property of a memory element and a method for manufacturing the same are proposed even in the case of forming a silicon film at a step portion formed by a surface of a substrate and a wiring formed over the substrate. The semiconductor device includes a plurality of the memory elements comprising a first electrode formed over a substrate having an insulating surface, sidewall insulating layer formed on side surface of the first electrode, a silicon film formed to cover the first electrode and the sidewall insulating layer, and a second electrode formed over the silicon film, and at least one of the first electrode and the second electrode is formed with a material being capable of being alloyed with the silicon film.

Claims

1. A semiconductor device comprising:

a first semiconductor layer over an insulating surface;

a second semiconductor layer over the insulating surface;

a gate electrode over the first semiconductor layer with a first insulating layer interposed therebetween;

a first electrode over the second semiconductor layer with a second insulating layer interposed therebetween, the first electrode being provided in the same layer as the gate electrode;

a sidewall insulating layer on a side surface of the first electrode, wherein the sidewall insulating layer is provided over and in contact with the insulating surface, and wherein the sidewall insulating layer has an inner side surface which contacts the side surface of the first electrode and an outer side surface opposite to the inner side surface;

a source electrode and a drain electrode over and in contact with the first semiconductor layer;

a third semiconductor layer over the first electrode and the sidewall insulating layer, wherein the third semiconductor layer is provided over and in contact with the insulating surface, and wherein the third semiconductor layer is provided in contact with the outer side surface of the sidewall insulating layer so that the sidewall insulating layer is interposed between the first electrode and the third semiconductor layer; and

a second electrode over the first electrode with the third semiconductor layer interposed therebetween,

wherein the third semiconductor layer crosses the first electrode,

wherein a material of the first electrode is the same as a material of the gate electrode;

wherein a material of the second electrode is the same as a material of the source electrode and the drain electrode,

wherein the first electrode, the sidewall insulating layer, the third semiconductor layer, and the second electrode are included in a memory element, and

wherein the memory element is capable of changing its state from a first state to a second state upon an application of a voltage, where a resistance between the first electrode and the second electrode is higher in the first state than in the second state.

2. The semiconductor device according to claim 1,

wherein at least one of the first electrode and the second electrode comprises a material being capable of being alloyed with the third semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the sidewall insulating layer has a curved surface, and

wherein the sidewall insulating layer is in contact with the third semiconductor layer at the curved surface.

4. The semiconductor device according to claim 1,

wherein at least one of the first electrode and the second electrode comprises a material including at least one of elements selected from Ti, W, Ni, Cr, Mo, Ta, Co, Zr, V, Pd, Hf, Pt, and Fe.

5. The semiconductor device according to claim 1, further comprising a substrate with the insulating surface,

wherein the substrate with the insulating surface is a glass substrate, a plastic substrate, a semiconductor substrate, or a sheet of paper.

12. The semiconductor device according to claim 1,

wherein the sidewall insulating layer has a curved surface, and

wherein the sidewall insulating layer is in contact with the semiconductor layer at the curved surface.

13. The semiconductor device according to claim 1,

wherein at least one of the first electrode and the second electrode comprises a material including at least one of elements selected from Ti, W, Ni, Cr, Mo, Ta, Co, Zr, V, Pd, Hf, Pt, and Fe.

14. The semiconductor device according to claim 1, further comprising a substrate with the insulating surface.

15. The semiconductor device according to claim 1, further comprising:

a connection electrode electrically connected to the transistor; and

an antenna electrically connected to the connection electrode;

wherein the connection electrode comprises the same material as at least one of the second electrode, the source electrode and the drain electrode.

17. The semiconductor device according to claim 14,

wherein the substrate with the insulating surface is a glass substrate, a plastic substrate, a semiconductor substrate, or a sheet of paper.

33. The semiconductor device according to claim 1,

wherein the second electrode is provided in the same layer as the source electrode and the drain electrode.

36. The semiconductor device according to claim 1, further comprising:

a connection electrode provided in the same layer as the second electrode; and

an antenna electrically connected to the connection electrode.

6. A semiconductor device comprising:

a transistor including a gate electrode, a source electrode, and a drain electrode; and

a memory element including;

a first electrode over and in contact with an insulating surface;

a sidewall insulating layer over and in contact with the insulating surface, wherein the sidewall insulating layer has a cross-sectional shape comprising a first layer and a second layer with the first electrode interposed therebetween, and wherein each of the first layer and the second layer has an inner side surface which contacts a side surface of the first electrode and an outer side surface opposite to the inner side surface;

a semiconductor layer over the first electrode and the sidewall insulating layer, wherein the semiconductor layer is provided in contact with the outer side surface of the first layer and the outer side surface of the second layer so that the sidewall insulating layer is interposed between the first electrode and the semiconductor layer; and

a second electrode over the first electrode with the semiconductor layer and the sidewall insulating layer interposed therebetween,

wherein the gate electrode comprises the same material as the first electrode,

wherein the gate electrode is provided in the same layer as the first electrode,

wherein at least one of the source electrode and the drain electrode comprises the same material as the second electrode, and

wherein at least one of the first electrode and the second electrode comprises a material being capable of being alloyed with the semiconductor layer.

7. The semiconductor device according to claim 6,

wherein the sidewall insulating layer has a curved surface, and

wherein the sidewall insulating layer is in contact with the semiconductor layer at the curved surface.

8. The semiconductor device according to claim 6,

wherein at least one of the first electrode and the second electrode comprises a material including at least one of elements selected from Ti, W, Ni, Cr, Mo, Ta, Co, Zr, V, Pd, Hf, Pt, and Fe.

9. The semiconductor device according to claim 6, further comprising a substrate with the insulating surface.

10. The semiconductor device according to claim 6, further comprising:

a connection electrode electrically connected to the transistor; and

an antenna electrically connected to the connection electrode;

wherein the connection electrode comprises the same material as at least one of the second electrode, the source electrode and the drain electrode.

16. The semiconductor device according to claim 9,

wherein the substrate with the insulating surface is a glass substrate, a plastic substrate, a semiconductor substrate, or a sheet of paper.

18. The semiconductor device according to claim 6,

wherein the semiconductor layer comprises an oxide semiconductor.

20. The semiconductor device according to claim 6,

wherein the first electrode is a single layer, and

wherein the semiconductor layer is on and in contact with a top surface of the first electrode.

22. The semiconductor device according to claim 6,

wherein the semiconductor layer is in contact with the first electrode at an intersection of the first electrode and the second electrode.

24. The semiconductor device according to claim 6,

wherein the second electrode is a single layer.

26. The semiconductor device according to claim 6, wherein the memory element is capable of changing its state from a first state to a second state upon an application of a voltage, and

where a resistance between the first electrode and the second electrode is higher in the first state than in the second state.

28. The semiconductor device according to claim 6, further comprising a plurality of transistors and a plurality of memory elements,

wherein each of the plurality of transistors is the transistor, and

wherein each of the plurality of memory elements is the memory element.

34. The semiconductor device according to claim 6,

wherein the second electrode is provided in the same layer as the source electrode and the drain electrode.

37. The semiconductor device according to claim 10,

wherein the connection electrode is provided in the same layer as the second electrode.

11. A semiconductor device comprising:

a transistor including a gate electrode, a source electrode, and a drain electrode; and

a memory element including;

a first electrode over and in contact with an insulating surface;

a sidewall insulating layer on a side surface of the first electrode, wherein the sidewall insulating layer is provided over and in contact with the insulating surface, and wherein the sidewall insulating layer has an inner side surface which contacts the side surface of the first electrode and an outer side surface opposite to the inner side surface;

a semiconductor layer over the first electrode and the sidewall insulating layer, wherein the semiconductor layer is provided in contact with the outer side surface of the sidewall insulating layer so that the sidewall insulating layer is interposed between the first electrode and the semiconductor layer; and

a second electrode over the first electrode with the semiconductor layer and the sidewall insulating layer interposed therebetween;

wherein the semiconductor layer crosses the first electrode,

wherein the gate electrode comprises the same material as the first electrode,

wherein the gate electrode is provided in the same layer as the first electrode,

wherein at least one of the source electrode and the drain electrode comprises the same material as the second electrode, and

wherein at least one of the first electrode and the second electrode comprises a material being capable of being alloyed with the semiconductor layer.

19. The semiconductor device according to claim 11,

wherein the semiconductor layer comprises an oxide semiconductor.

21. The semiconductor device according to claim 11,

wherein the first electrode is a single layer, and

wherein the semiconductor layer is on and in contact with a top surface of the first electrode.

23. The semiconductor device according to claim 11,

wherein the semiconductor layer is in contact with the first electrode at an intersection of the first electrode and the second electrode.

25. The semiconductor device according to claim 11,

wherein the second electrode is a single layer.

27. The semiconductor device according to claim 11, wherein the memory element is capable of changing its state from a first state to a second state upon an application of a voltage, and

where a resistance between the first electrode and the second electrode is higher in the first state than in the second state.

29. The semiconductor device according to claim 11, further comprising a plurality of transistors and a plurality of memory elements,

wherein each of the plurality of transistors is the transistor, and

wherein each of the plurality of memory elements is the memory element.

35. The semiconductor device according to claim 11,

wherein the second electrode is provided in the same layer as the source electrode and the drain electrode.

30. A semiconductor device comprising:

a first semiconductor layer over an insulating surface;

a second semiconductor layer over the insulating surface;

a gate electrode over the first semiconductor layer with a first insulating layer interposed therebetween;

a first electrode over the second semiconductor layer with a second insulating layer interposed therebetween, the first electrode being provided in the same layer as the gate electrode;

a first sidewall insulating layer on a side surface of the gate electrode;

a second sidewall insulating layer on a side surface of the first electrode, wherein a material of the second sidewall insulating layer is the same as a material of the first sidewall insulating layer;

a source electrode and a drain electrode over and in contact with the first semiconductor layer;

a third semiconductor layer in contact with the first electrode and the second sidewall insulating layer;

a second electrode over and in contact with the third semiconductor layer,

wherein a material of the first electrode is the same as a material of the gate electrode;

wherein a material of the second electrode is the same as a material of the source electrode and the drain electrode,

wherein at least one of the first electrode and the second electrode comprises a material being capable of being alloyed with the third semiconductor layer.

31. The semiconductor device according to claim 30,

wherein the third semiconductor layer comprises an oxide semiconductor.

32. The semiconductor device according to claim 30,

wherein the second electrode is provided in the same layer as the source electrode and the drain electrode.